參數(shù)資料
型號: ADSP-21262SKSTZ200
廠商: ANALOG DEVICES INC
元件分類: 數(shù)字信號處理
英文描述: SHARC Processor
中文描述: 16-BIT, 66.67 MHz, OTHER DSP, PQFP144
封裝: LEAD FREE, MS-026BFB, LQFP-144
文件頁數(shù): 31/44頁
文件大小: 1295K
代理商: ADSP-21262SKSTZ200
ADSP-21262
Rev. A
|
Page 31 of 44
|
May 2004
Figure 22. Serial Ports
DRIVE EDGE
DAI_P[20:1]
SCLK (INT)
DRIVE EDGE
DRIVE EDGE
SCLK
DAI_P[20:1]
SCLK (EXT)
t
DDTTE
t
DDTEN
t
DDTIN
DAI_P[20:1]
(DATA CHANNEL A/B)
DAI_P[20:1]
(DATA CHANNEL A/B)
DAI_P[20:1]
(SCLK)
DAI_P[20:1]
(FS)
DRIVE EDGE
SAMPLE EDGE
DATA RECEIVE— INTERNAL CLOCK
DATA RECEIVE— EXTERNAL CLOCK
DRIVE EDGE
SAMPLE EDGE
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF SCLK (EXTERNAL), SCLK (INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE.
t
SDRI
t
HDRI
t
SFSI
t
HFSI
t
DFSI
t
HOFSI
t
SCLKIW
t
SDRE
t
HDRE
t
SFSE
t
HFSE
t
DFSE
t
SCLKW
t
HOFSE
DAI_P[20:1]
(DATA CHANNEL A/B)
t
DDTI
DRIVE EDGE
SAMPLE EDGE
DATA TRANSMIT — INTERNAL CLOCK
t
SFSI
t
HFSI
t
DFSI
t
HOFSI
t
SCLKIW
t
HDTI
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF SCLK (EXTERNAL), SCLK (INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE.
t
DDTE
DRIVE EDGE
SAMPLE EDGE
DATA TRANSMIT — EXTERNAL CLOCK
t
SFSE
t
HFSE
t
DFSE
t
HOFSE
t
SCLKW
t
HDTE
DAI_P[20:1]
(SCLK)
DAI_P[20:1]
(FS)
DAI_P[20:1]
(DATA CHANNEL A/B)
DAI_P[20:1]
(SCLK)
DAI_P[20:1]
(FS)
DAI_P[20:1]
(DATA CHANNEL A/B)
DAI_P[20:1]
(SCLK)
DAI_P[20:1]
(FS)
DAI_P[20:1]
(DATA CHANNEL A/B)
相關PDF資料
PDF描述
ADSP-21262 SHARC Processor
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ADSP-21262SKBCZ200 SHARC Processor
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相關代理商/技術參數(shù)
參數(shù)描述
ADSP-21262SKSTZ200 制造商:Analog Devices 功能描述:IC 32-BIT DSP
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