參數(shù)資料
型號(hào)： ADSP-21262SKSTZ200
廠商： ANALOG DEVICES INC
元件分類： 數(shù)字信號(hào)處理
英文描述： SHARC Processor
中文描述： 16-BIT, 66.67 MHz, OTHER DSP, PQFP144
封裝： LEAD FREE, MS-026BFB, LQFP-144
文件頁(yè)數(shù)： 20/44頁(yè)
文件大?。?/td> 1295K
代理商： ADSP-21262SKSTZ200
Rev. A
|
Page 20 of 44
|
May 2004
ADSP-21262
Reset
Interrupts
The following timing specification applies to the FLAG0,
FLAG1, and FLAG2 pins when they are configured as IRQ0,
IRQ1, and IRQ2 interrupts. Also applies to DAI_P[20:1] pins
when configured as interrupts.
Core Timer
The following timing specification applies to FLAG3 when it is
configured as the core timer (CTIMER).
Table 11. Reset
Parameter
Timing Requirements
t
WRST
t
SRST
Min
Max
Unit
RESET Pulse Width Low
1
RESET Setup Before CLKIN Low
1
Applies after the power-up sequence is complete. At power-up, the processor's internal phase-locked loop requires no more than 100
μ
s while RESET is low, assuming
stable VDD and CLKIN (not including start-up time of external clock oscillator).
4t
CK
8
ns
ns
Figure 9. Reset
CLKIN
RESET
t
WRST
t
SRST
Table 12. Interrupts
Parameter
Timing Requirement
t
IPW
Min
Max
Unit
IRQx Pulse Width
2 × t
CCLK
+ 2
ns
Figure 10. Interrupts
DAI_P20-1
(FLAG2-0)
(IRQ2-0)
t
IPW
Table 13. Core Timer
Parameter
Switching Characteristic
t
WCTIM
Min
Max
Unit
CTIMER Pulse Width
4 × t
CCLK
– 1
ns
Figure 11. Core Timer
FLAG3
(CTIMER)
t
WCTIM
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADSP-21262SKSTZ200 制造商:Analog Devices 功能描述:IC 32-BIT DSP
ADSP-21266 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC Embedded Processor
ADSP-21266_07 制造商:AD 制造商全稱:Analog Devices 功能描述:Embedded Processor
ADSP-21266KSTZ-1C 制造商:Analog Devices 功能描述:- Trays
ADSP-21266KSTZ-2C 制造商:Analog Devices 功能描述:- Trays
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