參數(shù)資料
型號(hào): ADSP-21261SKSTZ150
廠商: Analog Devices Inc
文件頁(yè)數(shù): 7/44頁(yè)
文件大?。?/td> 0K
描述: IC DSP 32BIT 150MHZ 144LQFP
產(chǎn)品培訓(xùn)模塊: SHARC Processor Overview
標(biāo)準(zhǔn)包裝: 60
系列: SHARC®
類(lèi)型: 浮點(diǎn)
接口: DAI,SPI
時(shí)鐘速率: 150MHz
非易失內(nèi)存: ROM(384 kB)
芯片上RAM: 128kB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 1.20V
工作溫度: 0°C ~ 70°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 144-LQFP
供應(yīng)商設(shè)備封裝: 144-LQFP(20x20)
包裝: 托盤(pán)
ADSP-21261
Rev. 0
|
Page 15 of 44
|
March 2006
ADSP-21261 SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
ELECTRICAL CHARACTERISTICS
Parameter
1
1 Specifications subject to change without notice.
Min
Max
Unit
VDDINT
Internal (Core) Supply Voltage
1.14
1.26
V
AVDD
Analog (PLL) Supply Voltage
1.14
1.26
V
VDDEXT
External (I/O) Supply Voltage
3.13
3.47
V
VIH
High Level Input Voltage2 @ VDDEXT = max
2 Applies to input and bidirectional pins: AD15–0, FLAG3–0, DAI_Px, SPICLK, MOSI, MISO, SPIDS, BOOTCFGx, CLKCFGx, RESET, TCK, TMS, TDI, and TRST.
2.0
VDDEXT + 0.5 V
VIL
Low Level Input Voltage
2 @ V
DDEXT = min
–0.5
+0.8
V
VIH_CLKIN
High Level Input Voltage3 @ VDDEXT = max
3 Applies to input pin CLKIN.
1.74
VDDEXT + 0.5 V
VIL_CLKIN
Low Level Input Voltage @ VDDEXT = min
–0.5
+1.19
V
TAMB
Ambient Operating Temperature
4, 5
4 See Thermal Characteristics on Page 38 for information on thermal specifications.
5 See Engineer-to-Engineer Note (No. 216) for further information.
0+70
°C
Parameter1
Test Conditions
Min
Max
Unit
VOH
High Level Output Voltage2
@ VDDEXT = min, IOH = –1.0 mA
3
2.4
V
VOL
Low Level Output Voltage
2
@ VDDEXT = min, IOL = 1.0 mA
3
0.4
V
IIH
High Level Input Current4, 5
@ VDDEXT = max, VIN = VDDEXT max
10
μA
IIL
Low Level Input Current
4
@ VDDEXT = max, VIN = 0 V
10
μA
IILPU
Low Level Input Current Pull-Up
5
@ VDDEXT = max, VIN = 0 V
200
μA
IOZH
Three-State Leakage Current 6, 7, 8
@ VDDEXT = max, VIN = VDDEXT max
10
μA
IOZL
Three-State Leakage Current
6
@ VDDEXT = max, VIN = 0 V
10
μA
IOZLPU
Three-State Leakage Current Pull-Up
7
@ VDDEXT = max, VIN = 0 V
200
μA
IDD-INTYP
Supply Current (Internal)9, 10, 11
tCCLK = 6.67 ns, VDDINT = 1.2 V, TAMB = +25
°C375
mA
AIDD
Supply Current (Analog)
11
AVDD = max
10
mA
CIN
Input Capacitance
12, 13
fIN = 1 MHz, TCASE = 25°C, VIN = 1.2 V
4.7
pF
1 Specifications subject to change without notice.
2 Applies to output and bidirectional pins: AD15–0, RD, WR, ALE, FLAG3–0, DAI_Px, SPICLK, MOSI, MISO, EMU, TDO, CLKOUT, and XTAL.
3 See Output Drive Currents on Page 37 for typical drive current capabilities.
4 Applies to input pins: SPIDS, BOOTCFGx, CLKCFGx, TCK, RESET, and CLKIN.
5 Applies to input pins with 22.5 k
Ω internal pull-ups: TRST, TMS, and TDI.
6 Applies to three-statable pins: FLAG3–0.
7 Applies to three-statable pins with 22.5 k
Ω pull-ups: AD15–0, DAI_Px, SPICLK, MISO, and MOSI.
8 Applies to open-drain output pins: EMU, MISO, and MOSI.
9 Typical internal current data reflects nominal operating conditions.
10See Engineer-to-Engineer Note (No. 216) for further information.
11Characterized, but not tested.
12Applies to all signal pins.
13Guaranteed, but not tested.
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