參數(shù)資料
型號(hào): ADSP-21261SKSTZ150
廠商: Analog Devices Inc
文件頁數(shù): 22/44頁
文件大?。?/td> 0K
描述: IC DSP 32BIT 150MHZ 144LQFP
產(chǎn)品培訓(xùn)模塊: SHARC Processor Overview
標(biāo)準(zhǔn)包裝: 60
系列: SHARC®
類型: 浮點(diǎn)
接口: DAI,SPI
時(shí)鐘速率: 150MHz
非易失內(nèi)存: ROM(384 kB)
芯片上RAM: 128kB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 1.20V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 144-LQFP
供應(yīng)商設(shè)備封裝: 144-LQFP(20x20)
包裝: 托盤
ADSP-21261
Rev. 0
|
Page 29 of 44
|
March 2006
Serial Ports
To determine whether communication is possible between two
devices at clock speed n, the specifications in Table 23, Table 24,
1) frame sync delay and frame sync setup and hold; 2) data delay
and data setup and hold; and 3) SCLK width.
Serial port signals (SCLK, FS, DxA,/DxB) are routed to the
DAI_P20–1 pins using the SRU. Therefore, the timing specifica-
tions provided below are valid at the DAI_P20–1 pins.
Table 23. Serial Ports—External Clock
Parameter
Min
Max
Unit
Timing Requirements
tSFSE
FS Setup Before SCLK
(Externally Generated FS in Either Transmit or Receive Mode)1
2.5
ns
tHFSE
FS Hold After SCLK
(Externally Generated FS in Either Transmit or Receive Mode)
1
2.5
ns
tSDRE
Receive Data Setup Before Receive SCLK1
2.5
ns
tHDRE
Receive Data Hold After SCLK1
2.5
ns
tSCLKW
SCLK Width
7
ns
tSCLK
SCLK Period
20
ns
Switching Characteristics
tDFSE
FS Delay After SCLK
(Internally Generated FS in Either Transmit or Receive Mode)2
7ns
tHOFSE
FS Hold After SCLK
(Internally Generated FS in Either Transmit or Receive Mode)2
2ns
tDDTE
Transmit Data Delay After Transmit SCLK2
7ns
tHDTE
Transmit Data Hold After Transmit SCLK2
2ns
1 Referenced to sample edge.
2 Referenced to drive edge.
Table 24. Serial Ports—Internal Clock
Parameter
Min
Max
Unit
Timing Requirements
tSFSI
FS Setup Before SCLK
(Externally Generated FS in Either Transmit or Receive Mode)1
6ns
tHFSI
FS Hold After SCLK
(Externally Generated FS in Either Transmit or Receive Mode)1
1.5
ns
tSDRI
Receive Data Setup Before SCLK1
6ns
tHDRI
Receive Data Hold After SCLK
1
1.5
ns
Switching Characteristics
tDFSI
FS Delay After SCLK (Internally Generated FS in Transmit Mode)
2
3ns
tHOFSI
FS Hold After SCLK (Internally Generated FS in Transmit Mode)
2
–1.0
ns
tDFSI
FS Delay After SCLK (Internally Generated FS in Receive Mode)
2
3ns
tHOFSI
FS Hold After SCLK (Internally Generated FS in Receive Mode)2
–1.0
ns
tDDTI
Transmit Data Delay After SCLK2
3ns
tHDTI
Transmit Data Hold After SCLK2
–1.0
ns
tSCLKIW
Transmit or Receive SCLK Width
0.5tSCLK – 2
0.5tSCLK + 2
ns
1 Referenced to the sample edge.
2 Referenced to drive edge.
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