參數(shù)資料
型號(hào): ADS1191IPBSR
廠商: Texas Instruments
文件頁(yè)數(shù): 52/67頁(yè)
文件大?。?/td> 0K
描述: IC AFE 16BIT 8KSPS 1CH 32TQFP
標(biāo)準(zhǔn)包裝: 1,000
位數(shù): 16
通道數(shù): 1
電壓 - 電源,模擬: 2.7 V ~ 5.25 V
電壓 - 電源,數(shù)字: 1.7 V ~ 3.6 V
封裝/外殼: 32-TQFP
供應(yīng)商設(shè)備封裝: 32-TQFP(5x5)
包裝: 帶卷 (TR)
Set CLKSEL Pin = 1
and Wait for Oscillator
to Wake Up
No
Analog/Digital Power-Up
// Follow Power-Up Sequencing
External
Clock
Yes
No
// If START is Tied High, After This Step
// DRDY Toggles at fMOD/256
Set CLKSEL Pin = 0 and
Provide External Clock
fCLK = 512 kHz
Set PWDN/RESET = 1
Wait for 1 s for
Power-On Reset
// Delay for Power-On Reset and Oscillator Start-Up
Issue Reset Pulse,
Wait for 18 tCLKs
Send SDATAC
Command
External Reference
Write Certain Registers,
Including Input Short
Set PDB_REFBUF = 1
and Wait for Internal
Reference To Settle
Set START = 1
RDATAC
Capture Data and
Check Noise
Set Test Signals
Capture Data and
Test Signals
// Activate DUT
//CS can be Either Tied Permanently Low
// Or Selectively Pulled Low Before Sending
// Commands or Reading/Sending Data From/To Device
// If Using Internal Reference, Send This Command
-- WREG CONFIG2 A0h
// Device Wakes Up in RDATAC Mode, so Send
// SDATAC Command so Registers can be Written
SDATAC
// DRATE = 500 SPS
WREG CONFIG1 02h
// Set All Channels to Input Short
WREG CHnSET 01h
// Activate Conversion
// After This Point DRDY Should Toggle at
// fCLK/256
// Put the Device Back in RDATAC Mode
RDATAC
// Look for DRDY and Issue 16 + 2
16 SCLKs
// Activate a (1 mV VREF/2.4) Square-Wave Test Signal
// On All Channels
SDATAC
WREG CONFIG2 A3h
WREG CHnSET 05h
RDATAC
// Look for DRDY and Issue 16 + 2
16 SCLKs
SBAS566A – DECEMBER 2011 – REVISED SEPTEMBER 2012
Figure 52. Initial Flow at Power-Up
56
Copyright 2011–2012, Texas Instruments Incorporated
Product Folder Links: ADS1191 ADS1192
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