參數(shù)資料
型號(hào): ADS1191IPBSR
廠商: Texas Instruments
文件頁(yè)數(shù): 28/67頁(yè)
文件大小: 0K
描述: IC AFE 16BIT 8KSPS 1CH 32TQFP
標(biāo)準(zhǔn)包裝: 1,000
位數(shù): 16
通道數(shù): 1
電壓 - 電源,模擬: 2.7 V ~ 5.25 V
電壓 - 電源,數(shù)字: 1.7 V ~ 3.6 V
封裝/外殼: 32-TQFP
供應(yīng)商設(shè)備封裝: 32-TQFP(5x5)
包裝: 帶卷 (TR)
Hi-Z
START
DRDY
CS
SCLK
DIN
DOUT
RDATAOpcode
Status Register+8-ChannelData(216Bits)
RDATAOpcode
SBAS566A – DECEMBER 2011 – REVISED SEPTEMBER 2012
SDATAC: Stop Read Data Continuous
This opcode cancels the Read Data Continuous mode. There is no restriction on the SCLK rate for this
command, but the following command must wait for 4 tCLK cycles.
RDATA: Read Data
Issue this command after DRDY goes low to read the conversion result (in Stop Read Data Continuous mode).
There is no restriction on the SCLK rate for this command, and there is no wait time needed for the subsequent
commands or data retrieval SCLKs. To retrieve data from the device after the RDATA command is issued, make
sure either the START pin is high or the START command is issued. When reading data with the RDATA
command, the read operation can overlap the occurrence of the next DRDY without data corruption. Figure 39
shows the recommended way to use the RDATA command. RDATA is best suited for ECG- and EEG-type
systems where register setting must be read or changed often between conversion cycles.
Figure 39. RDATA Usage
Sending Multi-Byte Commands
The ADS1191/2 serial interface decodes commands in bytes and requires 4 tCLK cycles to decode and execute.
Therefore, when sending multi-byte commands, a 4 tCLK period must separate the end of one byte (or opcode)
and the next.
Assume CLK is 512 kHz, then tSDECODE (4 tCLK) is 7.8125 s. When SCLK is 16 MHz, one byte can be
transferred in 500 ns. This byte transfer time does not meet the tSDECODE specification; therefore, a delay must be
inserted so the end of the second byte arrives 7.3125 s later. If SCLK is 1 MHz, one byte is transferred in 8 s.
Because this transfer time exceeds the tSDECODE specification, the processor can send subsequent bytes without
delay. In this later scenario, the serial port can be programmed to cease single-byte transfer per cycle to multiple
bytes.
34
Copyright 2011–2012, Texas Instruments Incorporated
Product Folder Links: ADS1191 ADS1192
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