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參數(shù)資料
| 型號： | ADS1191IPBSR |
| 廠商： | Texas Instruments |
| 文件頁數(shù)： | 18/67頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC AFE 16BIT 8KSPS 1CH 32TQFP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 位數(shù)： | 16 |
| 通道數(shù)： | 1 |
| 電壓 - 電源，模擬： | 2.7 V ~ 5.25 V |
| 電壓 - 電源，數(shù)字： | 1.7 V ~ 3.6 V |
| 封裝/外殼： | 32-TQFP |
| 供應(yīng)商設(shè)備封裝： | 32-TQFP（5x5） |
| 包裝： | 帶卷 (TR) |
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SBAS566A – DECEMBER 2011 – REVISED SEPTEMBER 2012
DATA FORMAT
The ADS1191/2 outputs 16 bits of data per channel in binary twos complement format, MSB first. The LSB has a
weight of VREF/(2
15 – 1). A positive full-scale input produces an output code of 7FFFh and the negative full-scale
input produces an output code of 8000h. The output clips at these codes for signals exceeding full-scale. Table 4
summarizes the ideal output codes for different input signals. All 16 bits toggle when the analog input is at
positive or negative full-scale.
Table 4. Ideal Output Code versus Input Signal
INPUT SIGNAL, VIN
(AINP – AINN)
IDEAL OUTPUT CODE(1)
≥ VREF
7FFFh
+VREF/(2
15 – 1)
0001h
0
0000h
–VREF/(2
15 – 1)
FFFFh
≤ –VREF (2
15/215 – 1)
8000h
(1)
Excludes effects of noise, linearity, offset, and gain error.
SPI INTERFACE
The SPI-compatible serial interface consists of four signals: CS, SCLK, DIN, and DOUT. The interface reads
conversion data, reads and writes registers, and controls the ADS1191/2 operation. The DRDY output is used as
a status signal to indicate when data are ready. DRDY goes low when new data are available.
Chip Select (CS)
Chip select (CS) selects the ADS1191/2 for SPI communication. CS must remain low for the entire duration of
the serial communication. After the serial communication is finished, always wait four or more tCLK cycles before
taking CS high. When CS is taken high, the serial interface is reset, SCLK and DIN are ignored, and DOUT
enters a high-impedance state. DRDY asserts when data conversion is complete, regardless of whether CS is
high or low.
Serial Clock (SCLK)
SCLK is the serial peripheral interface (SPI) serial clock. It is used to shift in commands and shift out data from
the device. The serial clock (SCLK) features a Schmitt-triggered input and clocks data on the DIN and DOUT
pins into and out of the ADS1191/2. Even though the input has hysteresis, it is recommended to keep SCLK as
clean as possible to prevent glitches from accidentally forcing a clock event. The absolute maximum limit for
SCLK is specified in the Serial Interface Timing table. When shifting in commands with SCLK, make sure that the
entire set of SCLKs is issued to the device. Failure to do so could result in the device serial interface being
placed into an unknown state, requiring CS to be taken high to recover.
For a single device, the minimum speed needed for the SCLK depends on the number of channels, number of
bits of resolution, and output data rate. (For multiple cascaded devices, see the Cascade Mode subsection of the
Multiple Device Configuration section.)
tSCLK < (tDR – 4 tCLK)/(NBITSNCHANNELS + 24)
(7)
For example, if the ADS1191/2 is used in a 500-SPS mode (two channels, 16-bit resolution), the minimum SCLK
speed is approximately 36 kHz.
Data retrieval can be done either by putting the device in RDATAC mode or by issuing a RDATA command for
data on demand. The above SCLK rate limitation applies to RDATAC. For the RDATA command, the limitation
applies if data must be read in between two consecutive DRDY signals. The above calculation assumes that
there are no other commands issued in between data captures. SCLK can only be twice the speed of fCLK during
register reads and writes. For faster SPI interface, use fCLK = 2.048 MHz and set the CLK_DIV register bit (in the
LOFF_STAT register) to '1'.
Copyright 2011–2012, Texas Instruments Incorporated
25
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