參數(shù)資料
型號: ADS1191IPBSR
廠商: Texas Instruments
文件頁數(shù): 32/67頁
文件大?。?/td> 0K
描述: IC AFE 16BIT 8KSPS 1CH 32TQFP
標準包裝: 1,000
位數(shù): 16
通道數(shù): 1
電壓 - 電源,模擬: 2.7 V ~ 5.25 V
電壓 - 電源,數(shù)字: 1.7 V ~ 3.6 V
封裝/外殼: 32-TQFP
供應商設備封裝: 32-TQFP(5x5)
包裝: 帶卷 (TR)
SBAS566A – DECEMBER 2011 – REVISED SEPTEMBER 2012
CONFIG2: Configuration Register 2
Address = 02h
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
PDB_LOFF_
1
PDB_REFBUF
VREF_4V
CLK_EN
0
INT_TEST
TEST_FREQ
COMP
Configuration Register 2 configures the test signal, clock, reference, and LOFF buffer.
Bit 7
Must be set to '1'
Bit 6
PDB_LOFF_COMP: Lead-off comparator power-down
This bit powers down the lead-off comparators.
0 = Lead-off comparators disabled (default)
1 = Lead-off comparators enabled
Bit 5
PDB_REFBUF: Reference buffer power-down
This bit powers down the internal reference buffer so that the external reference can be used.
0 = Reference buffer is powered down (default)
1 = Reference buffer is enabled
Bit 4
VREF_4V: Enables 4-V reference
This bit chooses between 2.42-V and 4.033-V reference.
0 = 2.42-V reference (default)
1 = 4.033-V reference
Bit 3
CLK_EN: CLK connection
This bit determines if the internal oscillator signal is connected to the CLK pin when an internal oscillator is used.
0 = Oscillator clock output disabled (default)
1 = Oscillator clock output enabled
Bit 2
Must be set to '0'
Bit 1
INT_TEST: Test signal selection
This bit determines whether the test signal is turned on or off.
0 = Off (default)
1 = On; amplitude = ±(VREFP – VREFN)/2420
Bit 0
TEST_FREQ: Test signal frequency.
This bit determines the test signal frequency.
0 = At dc (default)
1 = Square wave at 1 Hz
38
Copyright 2011–2012, Texas Instruments Incorporated
Product Folder Links: ADS1191 ADS1192
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