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參數(shù)資料
| 型號： | ADS1191IPBSR |
| 廠商： | Texas Instruments |
| 文件頁數(shù)： | 20/67頁 |
| 文件大小： | 0K |
| 描述： | IC AFE 16BIT 8KSPS 1CH 32TQFP |
| 標準包裝： | 1,000 |
| 位數(shù)： | 16 |
| 通道數(shù)： | 1 |
| 電壓 - 電源，模擬： | 2.7 V ~ 5.25 V |
| 電壓 - 電源，數(shù)字： | 1.7 V ~ 3.6 V |
| 封裝/外殼： | 32-TQFP |
| 供應商設備封裝： | 32-TQFP（5x5） |
| 包裝： | 帶卷 (TR) |
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GPIOPin
GPIOData(read)
GPIOData(write)
GPIOControl
DRDY
DOUT
SCLK
Bit 55
Bit 54
Bit 53
SBAS566A – DECEMBER 2011 – REVISED SEPTEMBER 2012
Figure 30 shows the relationship between DRDY, DOUT, and SCLK during data retrieval (in case of an
ADS1191/2 with a selected data rate that gives 16-bit resolution). DOUT is latched out at the rising edge of
SCLK. DRDY is pulled high at the falling edge of SCLK. Note that DRDY goes high on the first falling edge SCLK
regardless of the status of the CS signal and regardless of whether data are being retrieved from the device or a
command is being sent through the DIN pin.
Figure 30. DRDY with Data Retrieval (CS = 0)
GPIO
The ADS1191/2 have a total of two general-purpose digital I/O (GPIO) pins available in the normal mode of
operation. The digital I/O pins are individually configurable as either inputs or as outputs through the GPIOC bits
register. The GPIOD bits in the GPIO register control the level of the pins. When reading the GPIOD bits, the
data returned are the logic level of the pins, whether they are programmed as inputs or outputs. When the GPIO
pin is configured as an input, a write to the corresponding GPIOD bit has no effect. When configured as an
output, a write to the GPIOD bit sets the output value.
If configured as inputs, these pins must be driven (do not float). The GPIO pins are set as inputs after power-on
or after a reset. Figure 31 shows the GPIO port structure. The pins should be shorted to DGND with a series
resistor if not used.
Figure 31. GPIO Port Pin
Power-Down/Reset (PWDN/RESET)
The PWDN/RESET pins are shared. If PWDN/RESET is held low for longer than 29 tMODs, the device is powered
down. The implementation is such that the device is always reset when PWDN/RESET makes a transition from
high to low. If the device is powered down it is reset first and then if 210 clock elapses it is powered down. Hence,
when powering up the device from a power-down state, all registers must be rewritten.
There are two methods to reset the ADS1191/2: pull the PWDN/RESET pin low, or send the RESET opcode
command. When using the PWDN/RESET pin, take it low to force a reset. Make sure to follow the minimum
pulse width timing specifications before taking the PWDN/RESET pin back high. The RESET command takes
effect on the eighth SCLK falling edge of the opcode command. On reset it takes 18 tCLK cycles to complete
initialization of the configuration registers to the default states and start the conversion cycle. Note that an
internal RESET is automatically issued to the digital filter whenever the CONFIG1 register is set to a new value
with a WREG command.
Copyright 2011–2012, Texas Instruments Incorporated
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| ADS1191IRSMR | 制造商:Texas Instruments 功能描述:AFE General Purpose 1ADC 24-Bit 1.8V/3V 32-Pin VQFN EP T/R 制造商:Texas Instruments 功能描述:IC AFE 16BIT 8KSPS 1CH 32VQFN 制造商:Texas Instruments 功能描述:Low Pwr Int AFE for ECG App |
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| ADS1192ECG-FE | 功能描述:數(shù)據(jù)轉換 IC 開發(fā)工具 ADS1192 Demo Kit RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
| ADS1192IPBS | 功能描述:模數(shù)轉換器 - ADC Low Pwr Integ AFE RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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