參數(shù)資料
型號： ADM7008
廠商： Electronic Theatre Controls, Inc.
英文描述： Octal Ethernet 10/100M PHY
中文描述： 八路個10/100M以太網(wǎng)物理層
文件頁數(shù)： 21/92頁
文件大?。?/td> 981K
代理商： ADM7008
ADM7008
Interface Description
Pin #
Pin Name
Type
O,
8mA
Pin Description
0: Normal REFCLK clock path
1: REFCLK delay by 2 ns
Port 4 Carrier Sense/Receive Data Valid. CRSDV_P4 asserts
when the receive medium is non-idle. The assertion of
CRSDV_P4 is asynchronous to REFCLK. At the de-assertion
of carrier, CRSDV_P4 de-asserts synchronously to REFCLK
only on the first di-bit of RXD. If there is still data in the FIFO
not yet presented onto RXD, then on the second di-bit of RXD,
CRSDV_P4 is asserted synchronously to REFCLK. The
toggling of CRSDV_P4 on the first and second di-bit continues
until all the data in the FIFO is presented onto RXD.
CRSDV_P4 is asserted for the duration of carrier activity for a
false carrier event.
Not Used.
Not used in SMII Mode
125M Receive Clock. This pin acts as 125M receive clock
when ADM7008 is programmed to SS_SMII mode. All
SSS_SMII_RXD are synchronous to the rising edge of this
clock.
Note:
that clock on this pin will not be active during power on
reset due to power on setting.
Port 4 RMII Transmit Data. Transmit data for port 4 inputs the
di-bits that re transmitted and are driven synchronously to
REFCLK. Note that in 100Mb/s mode, TXD can change once
per REFCLK cycle, whereas in 10Mb/s mode, TXD must be
held steady for 10 consecutive REFCLK cycles.
Link and Activity LED/Port 4 SMII Transmit Data. TXD0 for port
4 inputs the data that is transmitted and is driven synchronously
to SMII_REFCLK (pin 70). In 100Mb/s mode, TXD0 inputs a
new 10-bit segment starting with SYNC. In 10Mb/s mode,
TXD0 must repeat each 10-bit segment 10 times.
TXD1_P4 acts as Port 4 Link/Activity LED in both SMII and
SS_SMII Mode. See LED Description for more detail.
Link and Activity LED/Port 4 SS_SMII Transmit Data. TXD0 for
port 4 inputs the data that is transmitted and is driven
synchronously to TXCLK (pin 70). In 100Mb/s mode, TXD0
inputs a new 10-bit segment starting with SYNC. In 10Mb/s
mode, TXD0 must repeat each 10-bit segment 10 times.
Port 4 Transmit Enable. Transmit Enable for port 4 indicates
that the di-bit on TXD is valid and it is driven synchronously to
REFCLK.
SMII 125M Reference Clock. In SMII Mode, this pin acts as
125M reference clock for all ports. All transmit and receive data
(include transmit enable and receive data valid) should be
synchronous to the rising edge of this clock.
ADMtek Inc.
2-9
RMII Mode
CRSDV_P4
SMII Mode
N/A
SS_SMII Mode
RXCLK
76, 77
RMII Mode
TXD[1:0]_P4
SMII Mode
LNKACT_P4,
SMII_TXD_P4
SS_SMII Mode
LNKACT_P4,
SSSMII_TXD_P4
I,
TTL,
PD
78
RMII Mode
TXEN_P4
SMII Mode
SMII_REFCLK
I,
TTL
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相關代理商/技術參數(shù)
參數(shù)描述
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