參數(shù)資料
型號： ADM7008
廠商： Electronic Theatre Controls, Inc.
英文描述： Octal Ethernet 10/100M PHY
中文描述： 八路個10/100M以太網物理層
文件頁數(shù)： 15/92頁
文件大小： 981K
代理商： ADM7008
ADM7008
Interface Description
Pin #
Pin Name
Type
Description
clock source for internal clock generator.
Note:
that when RSMODE1 is set to 1 (RMII mode), the input
of REFCLK should be 50M; when RSMODE1 is set to 0
(SMII or SS_SMII mode) the clock input on REFCLK
should be 125M
2.2.5 Clock Input, 3 pins
Pin #
115
Pin Name
XI/OSCI
Type
I, CTL Crystal/Oscillator input.
REFCLK_SEL = 0: 25M Crystal/Oscillator Input.
REFCLK_SEL = 1: Leave unconnected
O, CTL Crystal output. When 25M Oscillator is used, this pin should be
left unconnected. See XI/OSCI description above.
I/O,
16mA
LVTTL
REFCLK_SEL RSMODE1 REFCLK (Direction/Frequency)
0 0 Output/125 MHz
0 1 Output/50 MHz
1 0 Input/125 MHz with maximum 100ppm
1 1 Input/50 MHz with maximum 100ppm
Pin Description
116
XO
111
REFCLK
Reference clock.
Function on this pin is highly depended upon
the setting on REFCLK_SEL and RSMODE1:
2.2.6 RMII/SMII Interface, 48 pins
Pin #
51, 52
ADMtek Inc.
2-3
Pin Name
Power On
Setting
REC_10M_P7,
EN_AUTOMDIX
RMII Mode
RXD[1:0]_P7
SMII/SS_SMII
Mode
SPDLED_P7,
SMII_RXD_P7
Type
I/O,
8mA,
PD/PU
Pin Description
REC_10M: Value on RXD1_P7 will be latched by ADM7008
during power on reset as Port 7 10M Re-command value.
0: Recommend Port 7 to operate in 100M Mode
1: Recommend Port 7 to operate in 10M Mode
Auto MDIX Enable signal: Value on RXD0_P7 will be latched by
ADM7008 during power on reset as Auto MDIX function control
signal.
0: Disable all ports’ Auto MDIX function.
1: Enable all ports’ Auto MDIX function.
Port 7 RMII Receive Data. RXD[1:0] are the port 7 output di-
bits synchronously to REFCLK. Upon assertion of CRSDV_P,
RXD0 and RXD1 remain at 00 until valid data is output from the
FIFO onto RXD. 01 on RXD1 and RXD0 indicates the start of
valid data. If a false carrier or a symbol error is detected, RXD1
and RXD0 are set to 10 for the duration of the activity. Note
that in 100Mb/s mode RXD can change once per REFCLK
cycle, whereas in 10Mb/s mode RXD must be held steady for
10 consecutive REFCLK cycles.
Port 7 SMII Receive Data. RXD0 for the designated port
outputs data or in-band management information
synchronously to SMII REFCLK (pin 70). In 100Mb/s mode,
RXD0 outputs a new 10-bit segment starting with SYNC. In
10Mb/s mode, RXD0 must repeat each 10 bits segment 10
times. RXD1 for the designated port is acted as Speed Status
LED for port 7.
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