參數(shù)資料
型號： ADM7008
廠商： Electronic Theatre Controls, Inc.
英文描述： Octal Ethernet 10/100M PHY
中文描述： 八路個10/100M以太網(wǎng)物理層
文件頁數(shù)： 14/92頁
文件大小： 981K
代理商： ADM7008
ADM7008
Interface Description
2.2 Pin Description
Note:
For those pins, which have multiple functions, pin name is separated by slash (“/”).
If not specified, all signals are default to digital signals.
Please refer to section ‘1.5.3 Pin Type Descriptions
’
for an explanation of pin
abbreviations.
2.2.1 Twisted Pair Interface, 32 pins
Pin #
123, 5, 7, 17
19, 29, 31, 41
124, 4, 8, 16
20, 28, 32, 40
126, 2, 10, 14
22, 26, 34, 38
127, 1, 11, 23
23, 25, 35, 37
Pin Name
TXP[0:7]
Type
O,
Analog
O,
Analog
I, Analog Twisted Pair Receive Input Positive.
Description
Twisted Pair Transmit Output Positive.
TXN[0:7]
Twisted Pair Transmit Output Negative.
RXP[0:7]
RXN[0:7]
I, Analog Twisted Pair Receive Input Negative.
2.2.2 Ground and Power, 20 pins
Pin #
125, 3, 9, 15,
21, 27, 33, 39
118, 128, 12,
24, 36
122, 6, 18, 30,
42
120
Pin Name
GNDRT
Type
Analog
Ground
Analog
Power
Analog
Power
Analog
Ground
Analog
Power
Description
Analog Ground Pad
VCCAD
Analog 3.3V Power
VCCA2
Analog 1.8V Power
GNDRCV
Analog Ground used by Clock Generator module
121
VCCPLL2
Analog 1.8V Power used by Clock Generator module
2.2.3 Mode Setting
Pin #
43
Pin Name
RSMODE1
Type
I, PD
Description
RMII and SMII/SS_SMII mode select signal.
Dedicated input
provided by ADM7008 to determine the interface:
0: SMII or SS_SMII interface (See CRSDV_P6 power on setting
for more detail)
1: RMII interface
2.2.4 Clock Input Select
Pin #
48
ADMtek Inc.
2-2
Pin Name
REFCLK_SEL
Type
I, PD
Description
XI/XO and REFCLK clock select signal.
Dedicated input
provided by ADM7008 to determine the clock source for
ADM7008.
0: ADM7008 will use XI/XO as clock source for internal clock
generator. In this mode, REFCLK (pin 112) will output 50M
clock in RMII mode (RSMODE1 is set to 1) and 125M clock
in either SMII or SS_SMII mode (RSMODE1 is set to 0) \
1: ADM7008 will use the input of REFCLK (pin 112) as the
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