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參數(shù)資料
| 型號： | ADATE207BBPZ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | Quad Pin Timing Formatter |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA256 |
| 封裝： | ROHS COMPLIANT, MO-192-BAL-2, LBGA-256 |
| 文件頁數(shù)： | 9/36頁 |
| 文件大小： | 374K |
| 代理商： | ADATE207BBPZ |
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ADATE207
Pin No.
G20
Rev. 0 | Page 9 of 36
Mnemonic
DR_EN_CH3_N
Input/Output
1
D, O
Type
Differential
open-drain
Differential
input
Description
Inverted DCL Drive Enable Signal for Channel 3.
L20
LJ_CLK_P
D, I
Noninverted Low Jitter Clock Input. This pin
can be multiplexed onto DR_DATA outputs
for Channel 2 and Channel 3.
Inverted Low Jitter Clock Input. This pin can
be multiplexed onto DR_DATA outputs for
Channel 2 and Channel 3.
Noninverted DCL High Comparator Signal for
Channel 0. Differential signal is Logic 1 when
the DUT output is higher than V
OH
.
Inverted DCL High Comparator Signal for
Channel 0.
K19
LJ_CLK_N
D, I
Differential
Input
M3
COMP_H_CH0_P
D, I
Differential
input
terminated
Differential
input
terminated
Differential
input
terminated
Differential
input
terminated
Differential
input
terminated
Differential
input
terminated
Differential
input
terminated
Differential
input
terminated
Differential
input
terminated
Differential
input
terminated
Differential
input
terminated
Differential
input
terminated
Differential
input
terminated
Differential
Input
terminated
Differential
input
terminated
Differential
input
terminated
Analog
M2
COMP_H_CH0_N
D, I
J4
COMP_H_CH1_P
D, I
Noninverted DCL High Comparator Signal for
Channel 1. Differential signal is Logic 1 when
the DUT output is higher than V
OH
.
Inverted DCL High Comparator Signal for
Channel 1.
J3
COMP_H_CH1_N
D, I
M18
COMP_H_CH2_P
D, I
Noninverted DCL High Comparator Signal for
Channel 2. Differential signal is Logic 1 when
the DUT output is higher than V
OH
.
Inverted DCL High Comparator Signal for
Channel 2.
M19
COMP_H_CH2_N
D, I
J17
COMP_H_CH3_P
D, I
Noninverted DCL High Comparator Signal for
Channel 3. Differential signal is Logic 1 when
the DUT output is higher than V
OH
.
Inverted DCL High Comparator Signal for
Channel 3.
J18
COMP_H_CH3_N
D, I
L3
COMP_L_CH0_P
D, I
Noninverted DCL Low Comparator Signal for
Channel 0. Differential signal is Logic 1 when
the DUT output is higher than V
OL
.
Inverted Low Comparator Signal for Channel 0.
L4
COMP_L_CH0_N
D, I
H1
COMP_L_CH1_P
D, I
Noninverted DCL Low Comparator Signal for
Channel 1. Differential signal is Logic 1 when
the DUT output is higher than V
OL
.
Inverted Low Comparator Signal for Channel 1.
J2
COMP_L_CH1_N
D, I
L18
COMP_L_CH2_P
D, I
Noninverted DCL Low Comparator Signal for
Channel 2. Differential signal is Logic 1 when
the DUT output is higher than V
OL
.
Inverted Low Comparator Signal for Channel 2.
L17
COMP_L_CH2_N
D, I
H20
COMP_L_CH3_P
D, I
Noninverted DCL Low Comparator Signal for
Channel 3. Differential signal is Logic 1 when
the DUT output is higher than V
OL
.
Inverted Low Comparator Signal for Channel 3.
J19
COMP_L_CH3_N
D, I
M1
COMP_L_CH0_T
A, I, O
Center Tap. Center tap of two 50 Ω resistor
terminations for the low comparator
differential inputs of Channel 0.
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