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參數(shù)資料
| 型號： | ADATE207BBPZ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | Quad Pin Timing Formatter |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA256 |
| 封裝： | ROHS COMPLIANT, MO-192-BAL-2, LBGA-256 |
| 文件頁數(shù)： | 30/36頁 |
| 文件大?。?/td> | 374K |
| 代理商： | ADATE207BBPZ |
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ADATE207
Position
Bits[10:08]
Rev. 0 | Page 30 of 36
Description
PAT_DUTDATA2 Select. A binary encoded data field that selects which edge and which comparator
to drive out of the ADATE207 PAT_DUTDATAx[2] pin.
0x0 = Edge D0 low comparator.
0x1 = Edge D0 high comparator.
0x2 = Edge D1 low comparator.
0x3 = Edge D1 high comparator.
0x4 = Edge D2 low comparator.
0x5 = Edge D2 high comparator.
0x6 = Edge D3 low comparator.
0x7 = Edge D3 high comparator.
Not Used
PAT_DUTDATA1 Select. A binary encoded data field that selects which edge and which comparator
to drive out of the ADATE207 PAT_DUTDATAx[1] pin.
0x0 = Edge D0 low comparator.
0x1 = Edge D0 high comparator.
0x2 = Edge D1 low comparator.
0x3 = Edge D1 high comparator.
0x4 = Edge D2 low comparator.
0x5 = Edge D2 high comparator.
0x6 = Edge D3 low comparator.
0x7 = Edge D3 high comparator.
Not Used
PAT_DUTDATA0 Select. A binary encoded data field that selects which edge and which comparator
to drive out of the ADATE207 PAT_DUTDATAx[0] pin.
0x0 = Edge D0 low comparator.
0x1 = Edge D0 high comparator.
0x2 = Edge D1 low comparator.
0x3 = Edge D1 high comparator.
0x4 = Edge D2 low comparator.
0x5 = Edge D2 high comparator.
0x6 = Edge D3 low comparator.
0x7 = Edge D3 high comparator.
Reset State
0x0
Bit 07
Bits[06:04]
0
0x0
Bit 03
Bits[02:00]
0
0x0
CHIP-SPECIFIC (COMMON) REGISTERS
Name:
Address:
Type:
Software Resets
0x19
Write
Table 33. Software Resets
Position
Bit 15
Bits[14:04]
Bit 03
Description
DLL Ready. Indicates that the internal PLL and DLL are stable after a reset and/or MCLK change.
Not Used.
Error Registers Clear.
Writing a 1 to this bit creates a pulse to clear all the delay generation errors for all channels and
resets the edge generation logic.
Writing a 0 has no affect.
Accumulated Fail Registers Clear.
Writing a 1 to this bit creates a pulse to clear the accumulated fail registers for all channels.
Writing a 0 has no affect.
Reset State
Dynamic
0x000
0x0
Bit 02
0x0
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