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參數(shù)資料
| 型號： | ADATE207BBPZ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | Quad Pin Timing Formatter |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA256 |
| 封裝： | ROHS COMPLIANT, MO-192-BAL-2, LBGA-256 |
| 文件頁數(shù)： | 10/36頁 |
| 文件大?。?/td> | 374K |
| 代理商： | ADATE207BBPZ |
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ADATE207
Pin No.
H2
Rev. 0 | Page 10 of 36
Mnemonic
COMP_L_CH1_T
Input/Output
1
A, I, O
Type
Analog
Description
Center Tap. Center tap of two 50 Ω
r
esistor
terminations for the low comparator
differential inputs of Channel 1.
Center Tap. Center tap of two 50 Ω resistor
terminations for the low comparator
differential Inputs of Channel 2.
Center Tap. Center tap of two 50 Ω resistor
terminations for the low comparator
differential inputs of Channel 3.
Center Tap. Center tap of two 50 Ω resistor
terminations for the high comparator
differential inputs of Channel 0.
Center Tap. Center tap of two 50 Ω resistor
terminations for the high comparator
differential inputs of Channel 1.
Center Tap. Center tap of two 50 Ω resistor
terminations for the high comparator
differential inputs of Channel 2.
Center Tap. Center tap of two 50 Ω resistor
terminations for the high comparator
differential inputs of Channel 3.
Bidirectional Multiplexed Address/Data Bus
for CSR Register Access. Clocked by MCLK.
M20
COMP_L_CH2_T
A, I, O
Analog
H19
COMP_L_CH3_T
A, I, O
Analog
M4
COMP_H_CH0_T
A, I, O
Analog
H3
COMP_H_CH1_T
A, I, O
Analog
M17
COMP_H_CH2_T
A, I, O
Analog
H18
COMP_H_CH3_T
A, I, O
Analog
W15, V15, Y16, W16, Y17,
W17, U16, V17, U18, T17,
U19, U20, T19, T20, R18, R19
U13
CS_AD[15:0]
I, O
LVCMOS25
CS_AS
I
LVCMOS25
Address Strobe for the Address/Data Bus.
Clocked by MCLK.
Read/Write Bar Signal for the Address Data
Bus. High for reads. Clocked by MCLK.
Mode Pin for Clock Generation. Tie to Logic
low for normal operation.
Positive Portion of the Master Clock Signal.
Negative Portion of the Master Clock Signal.
Reset Bar. Active low power-on reset signal.
Scan Chain Data In. Tie to Logic high for
normal operation.
Scan Chain Data Out.
Scan Chain Clock. Tie to Logic high for
normal operation.
Scan Chain Mode. Tie to Logic high for
normal operation.
Active Low Scan Chain Reset. Tie to Logic low
for normal operation.
Controls the output current of the differential
open drain outputs.
Thermal Sensing Diode Anode. Force current
and measure voltage to measure die
temperature stability.
Must be connected to VSS.
No Connect. Must be left unconnected.
V14
CS_RW_B
I
LVCMOS25
Y15
CLKGEN_MD_EN
I
LVCMOS25
L1
K2
R4
D19
MCLK_P
MCLK_N
RESET_B
TDI
D, I
D, I
I
I
LVCMOS25
LVCMOS25
LVCMOS25
LVCMOS25
C8
A7
TDO
TCK
O
I
LVCMOS25
LVCMOS25
D18
TMS
I
LVCMOS25
E17
TRST_B
I
LVCMOS25
R1
REF_1K
A, I, O
Analog
P3
T_DIODE
A, I, O
Analog
T2
F2, F1, F19, F20, T1, R3, R2,
R20, N4, N17, P18
R17, U15, D9, D11, D12, D13,
U10, U9, V7, V5
U8, U6, T18, V16
C9, C11, C13, C15, V11, V9
A3 to A1
TESTMODE
NC
I
LVCMOS25
SHIELD
IOVSS
A, I, O, P
P
GND
GND
Connect to VSS.
Power, 0.0 V.
IOVDD
IOVDD
VSS
P
P
P
VDD
Power, 2.5 V.
Power, 2.5 V.
Power, 0.0 V
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