參數(shù)資料
型號： ADATE207BBPZ
廠商： ANALOG DEVICES INC
元件分類： 消費家電
英文描述： Quad Pin Timing Formatter
中文描述： SPECIALTY CONSUMER CIRCUIT, PBGA256
封裝： ROHS COMPLIANT, MO-192-BAL-2, LBGA-256
文件頁數(shù)： 8/36頁
文件大?。?/td> 374K
代理商： ADATE207BBPZ
ADATE207
Pin No.
D5
Rev. 0 | Page 8 of 36
Mnemonic
PAT_DATA_VALID
Input/Output
1
I
Type
LVCMOS25
Description
Indicates Pattern Bursting. When not
asserted, edges are disabled and the drive
and expect signals are static. Clocked by
MCLK.
Indicates the Start of a T0 Period. Clocked
by MCLK.
Indicates the Start of a C0 Period. Clocked
by MCLK.
Global Delay Input For All Edges. Clocked
by MCLK.
Differential Tristate Output. Noninverted TMU
ARM multiplexer output. High-Z when not
enabled.
Differential Tristate Output. Inverted TMU
ARM multiplexer output. High-Z when not
enabled.
Differential Tristate Output. Noninverted TMU
START multiplexer output. High-Z when not
enabled.
Differential Tristate Output. Inverted TMU
START multiplexer output. High-Z when not
enabled.
Noninverted TMU STOP Multiplexer Output.
Differential tristate output. High-Z when not
enabled.
Inverted TMU STOP Multiplexer Output.
Differential tristate output. High-Z when not
enabled.
Noninverted DCL Drive Data Signal for
Channel 0.
Inverted DCL Drive Data Signal for Channel 0.
F3
PER_EARLY_T0EN
I
LVCMOS25
E1
PER_EARLY_C0EN
I
LVCMOS25
C4, D3, E4, D2, D1, E3, F4, E2
INPUT_DELAY[7:0]
I
LVCMOS25
F18
TMU_ARM_P
D, O
Differential
open-drain
E20
TMU_ARM_N
D, O
Differential
open-drain
E19
TMU_START_P
D, O
Differential
open-drain
F17
TMU_START_N
D, O
Differential
open-drain
E18
TMU_STOP_P
D, O
Differential
open-drain
D20
TMU_STOP_N
D, O
Differential
open-drain
P2
DR_DATA_CH0_P
D, O
Differential
open-drain
Differential
open-drain
Differential
open-drain
Differential
open-drain
Differential
open-drain
Differential
open-drain
Differential
open-drain
Differential
open-drain
Differential
open-drain
Differential
open-drain
Differential
open-drain
Differential
open-drain
Differential
open-drain
Differential
open-drain
Differential
open-drain
P1
DR_DATA_CH0_N
D, O
G3
DR_DATA_CH1_P
D, O
Noninverted DCL Drive Data Signal for
Channel 1.
Inverted DCL Drive Data Signal for Channel 1.
H4
DR_DATA_CH1_N
D, O
P19
DR_DATA_CH2_P
D, O
Noninverted DCL Drive Data Signal for
Channel 2.
Inverted DCL Drive Data Signal for Channel 2.
P20
DR_DATA_CH2_N
DO
G18
DR_DATA_CH3_P
D, O
Noninverted DCL Drive Data Signal for
Channel 3.
Inverted DCL Drive Data Signal for Channel 3.
H17
DR_DATA_CH3_N
D, O
N3
DR_EN_CH0_P
D, O
Noninverted DCL Drive Enable Signal for
Channel 0.
Inverted DCL Drive Enable Signal for Channel 0.
N2
DR_EN_CH0_N
D, O
G2
DR_EN_CH1_P
D, O
Noninverted DCL Drive Enable Signal for
Channel 1.
Inverted DCL Drive Enable Signal for Channel 1.
G1
DR_EN_CH1_N
D, O
N18
DR_EN_CH2_P
D, O
Noninverted DCL Drive Enable Signal for
Channel 2.
Inverted DCL Drive Enable Signal for Channel 2.
N19
DR_EN_CH2_N
D, O
G19
DR_EN_CH3_P
D, O
Noninverted DCL Drive Enable Signal for
Channel 3.
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