參數(shù)資料
型號(hào)： ADATE207BBPZ
廠商： ANALOG DEVICES INC
元件分類： 消費(fèi)家電
英文描述： Quad Pin Timing Formatter
中文描述： SPECIALTY CONSUMER CIRCUIT, PBGA256
封裝： ROHS COMPLIANT, MO-192-BAL-2, LBGA-256
文件頁(yè)數(shù)： 16/36頁(yè)
文件大?。?/td> 374K
代理商： ADATE207BBPZ
ADATE207
After the power and MCLK inputs are stable, the device must be
reset using the hard reset and error reset bits. The soft reset can
be used to initialize registers at any time and does not reset the
PLL or FIFOs.
Rev. 0 | Page 16 of 36
There are six rules of reset.
Rule 1—on power up, keep the hard reset pin (RESET_B)
asserted.
Rule 2—if MCLK is unstable, keep the hard reset pin
(RESET_B) asserted.
Rule 3—after MCLK is stable, keep the hard reset pin
(RESET_B) asserted for at least 20 μs.
Rule 4—after the 20 μs of Rule 3 has elapsed, assert the error
reset bit (Bit 03 in Register 0x19).
Rule 5—the hard reset signal (RESET_B) can be asserted
asynchronously to MCLK, but upon deassertion, must make
setup and hold requirements upon the MCLK.
Rule 6—the minimum pulse width of RESET_B must be at least
three MCLK periods.
Table 11. Comparison Between Normal Mode and Clock Generation Mode
Normal Mode (CLKGEN_MD_EN=0)
Period Start
A single signal for all four channels, I_PER_EARLY_T0EN.
Clock Generator Mode(CLKGEN_MD_EN=1)
Four signals, one per channel; PAT_MASK[N] operates
as a period start signal for channel N.
Waveform memory location is fixed at Address 0.
Waveform
Memory Selection
Input Delay
Each channel N is selected via the I_PAT_PATDATA_N vector
every rising edge of I_MCLK.
A single vector adjust input delay for all channels,
INPUT_DELAY.
Four vectors are available, one per channel. For each
Channel N, PAT_PATDATA_N operates as
INPUT_DELAY for Channel N.
No masking of fail operations is available.
Fail Masking
Edge N for all channels can mask the fail operation every
rising edge of I_MCLK via PAT_MASK[N].
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