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參數(shù)資料
| 型號： | AD9920ABBCZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 79/112頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PROCESSOR CCD 12BIT 105CSPBGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 12 |
| 電壓 - 電源，模擬： | 1.6 V ~ 2 V |
| 電壓 - 電源，數(shù)字： | 1.6 V ~ 2 V |
| 封裝/外殼： | 105-LFBGA，CSPBGA |
| 供應(yīng)商設(shè)備封裝： | 105-CSPBGA（8x8） |
| 包裝： | 管件 |
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AD9920A
Rev. B | Page 69 of 112
COMPLETE EXPOSURE/READOUT OPERATION
USING PRIMARY COUNTER AND GPO SIGNALS
Note that if the mode registers are changed to be VD updated,
as shown in the Mode Registers section and in Figure 63, the
mode update is delayed by one additional field. This should be
accounted for in selecting the number of fields to cycle and in
determining which VD location to write to the mode registers.
1.
The primary counter is used to control the masking
of VSG and SUBCK during exposure/readout. The
PRIMARY_MAX register (Address 0x71) should be set
equal to the total number of fields used for exposure and
readout. In this example, PRIMARY_MAX = 5.
The SUBCK masking should not occur immediately at
the next VD edge (Step 2) because this would define an
exposure time that begins in the previous field. Write to
the PRIMARY_DELAY register (Address 0x72) to delay
the masking of VSG and SUBCK pulses in the first
exposure field. In this example, PRIMARY_DELAY = 1.
Write to the SUBCKMASK_NUM register (Address 0x74) to
specify the number of fields to mask SUBCK while the CCD
data is read. In this example, SUBCKMASK_NUM = 4.
Write to the SGMASK_NUM register (Address 0x74) to
specify the number of fields to mask VSG outputs during
exposure. In this example, SGMASK_NUM = 1.
Write to the PRIMARY_ACTION register (Address 0x70)
to trigger the GP1 (STROBE), GP2 (MSHUT), and GP3
(VSUB) signals and to start the expose/read operation.
Write to the mode registers to configure the next five fields.
The first two fields during exposure are the same as the
current draft mode fields, and the following three fields are
the still image frame readout fields. The register settings
for the draft mode field and the three readout fields are
previously programmed. Note that if the mode registers are
changed to VD updated, only one field of exposure should
be included (the second one) because the mode settings are
delayed an extra field.
2.
VD/HD falling edge updates the serial writes from 1.
3.
GP3 (VSUB) output turns on at the field/line/pixel specified.
In Figure 90, VSUB Example 1 and Example 2 use
GP3TOG1_FD = 1.
4.
GP1 (STROBE) output turns on and off at the location
specified.
5.
GP2 (MSHUT) output turns off at the location specified.
6.
The next VD falling edge automatically starts the first
read field.
7.
The next VD falling edge automatically starts the second
read field.
8.
The next VD falling edge automatically starts the third
read field.
9.
Write to the mode register to reconfigure the single draft
mode field timing. Note that if the mode registers are changed
to VD updated, this write should occur one field earlier.
10. VD/HD falling edge updates the serial writes from 9.
VSG outputs return to draft mode timing. SUBCK output
resumes operation. GP2 (MSHUT) output returns to the
on position (active or open). GP3 (VSUB) output returns
to the off position (inactive).
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9920ABBCZRL | 功能描述:IC PROCESSOR CCD 12BIT 105CSPBGA RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模擬前端 (AFE) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):- 通道數(shù):2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數(shù)字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
| AD9920BBCZ | 制造商:Analog Devices 功能描述: |
| AD9920BBCZRL | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| AD9921BBCZ | 制造商:Analog Devices 功能描述: |
| AD9921BBCZRL | 制造商:Analog Devices 功能描述: |
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