參數(shù)資料
型號： AD9920ABBCZ
廠商： Analog Devices Inc
文件頁數(shù)： 43/112頁
文件大小： 0K
描述： IC PROCESSOR CCD 12BIT 105CSPBGA
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 12
電壓 - 電源，模擬： 1.6 V ~ 2 V
電壓 - 電源，數(shù)字： 1.6 V ~ 2 V
封裝/外殼： 105-LFBGA，CSPBGA
供應(yīng)商設(shè)備封裝： 105-CSPBGA（8x8）
包裝： 管件
AD9920A
Rev. B | Page 36 of 112
Register
Length
(Bits)
Description
VREPB_ODD
13
Number of repetitions for the V-pattern Group B for odd lines.
VREPC_ODD
13
Number of repetitions for the V-pattern Group C for odd lines.
VREPD_ODD
13
Number of repetitions for the V-pattern Group D for odd lines.
VREPB_EVEN
13
Number of repetitions for the V-pattern Group B for even lines.
VREPC_EVEN
13
Number of repetitions for the V-pattern Group C for even lines.
VREPD_EVEN
13
Number of repetitions for the V-pattern Group D for even lines.
FREEZE1
13
Pixel location where the V-outputs freeze or hold (see VMASK_EVEN and VMASK_ODD). Also used as
VALTSEL0_EVEN, Bits[12:0] register when special VSEQALT_EN mode is enabled.
FREEZE2
13
Pixel location where the V-outputs freeze or hold (see VMASK_EVEN and VMASK_ODD). Also used as
VALTSEL1_EVEN, Bits[12:0] register when special VSEQALT_EN mode is enabled.
FREEZE3
13
Pixel location where the V-outputs freeze or hold (see VMASK_EVEN and VMASK_ODD). Also used as
VALTSEL0_ODD, Bits[12:0] register when special VSEQALT_EN mode is enabled.
FREEZE4
13
Pixel location where the V-outputs freeze or hold (see VMASK_EVEN and VMASK_ODD). Also used as
VALTSEL1_ODD, Bits[12:0] register when special VSEQALT_EN mode is enabled.
RESUME1
13
Pixel location where the V-outputs resume operation (see VMASK_EVEN and VMASK_ODD). Also used as
VALTSEL0_EVEN, Bits[17:13] register when special VSEQALT_EN mode is enabled.
RESUME2
13
Pixel location where the V-outputs resume operation (see VMASK_EVEN and VMASK_ODD). Also used as
VALTSEL1_EVEN, Bits[17:13] register when special VSEQALT_EN mode is enabled.
RESUME3
13
Pixel location where the V-outputs resume operation (see VMASK_EVEN and VMASK_ODD). Also used as
VALTSEL0_ODD, Bits[17:13] register when special VSEQALT_EN mode is enabled.
RESUME4
13
Pixel location where the V-outputs resume operation (see VMASK_EVEN and VMASK_ODD). Also used as
VALTSEL1_ODD, Bits[17:13] register when special VSEQALT_EN mode is enabled.
LASTREPLEN_A
13
Separate length for last repetition of vertical pulses for Group A. Must be enabled using LASTREPLEN_EN.
Should be programmed to a value equal to the VLENA register.
LASTREPLEN_B
13
Separate length for last repetition of vertical pulses for Group B. Must be enabled using LASTREPLEN_EN.
Should be programmed to a value equal to the VLENB register.
LASTREPLEN_C
13
Separate length for last repetition of vertical pulses for Group C. Must be enabled using LASTREPLEN_EN.
Should be programmed to a value equal to the VLENC register.
LASTREPLEN_D
13
Separate length for last repetition of vertical pulses for Group D. Must be enabled using LASTREPLEN_EN.
Should be programmed to a value equal to the VLEND register.
VSEQALT_EN
1
Special V-sequence alternation mode is enabled when this register is programmed high.
VALTSEL0_EVEN
18
Select lines for special V-sequence alternation mode for even lines. Used to concatenate VPAT Group A, Group B,
Group C, and Group D into unique merged patterns. Setting is used to specify one segment, with up to a maxi-
mum of 18 segments. (The FREEZE/RESUME registers function as VALTSEL when VSEQALT_EN is enabled.)
VALTSEL1_EVEN
18
Select lines for special V-sequence alternation mode for even lines. Used to concatenate VPAT Group A, Group B,
Group C, and Group D into unique merged patterns. Setting is used to specify one segment, with up to a maxi-
mum of 18 segments. (The FREEZE/RESUME registers function as VALTSEL when VSEQALT_EN is enabled.)
VALTSEL0_ODD
18
Select lines for special V-sequence alternation mode for odd lines. Used to concatenate VPAT Group A, Group B,
Group C, and Group D into unique merged patterns. Setting is used to specify one segment, with up to a maxi-
mum of 18 segments. (The FREEZE/RESUME registers function as VALTSEL when VSEQALT_EN is enabled.)
VALTSEL1_ODD
18
Select lines for special V-sequence alternation mode for odd lines. Used to concatenate VPAT Group A, Group B,
Group C, and Group D into unique merged patterns. Setting is used to specify one segment, with up to a maxi-
mum of 18 segments. (The FREEZE/RESUME registers function as VALTSEL when VSEQALT_EN is enabled.)
SPC_PAT_EN
3
Enable special V-pattern to be inserted into one repetition of a VPATA series.
SPC_PAT_EN, Bit 0: set to 1 to enable VPATB to be used as special pattern insertion.
SPC_PAT_EN, Bit 1: set to 1 to enable VPATC to be used as special pattern insertion.
SPC_PAT_EN, Bit 2: set to 1 to enable VPATD to be used as special pattern insertion.
SEQ_ALT_INC
1
0 = normal operation.
1 = automatically increments the sequence number at the end of the line, unless a sequence change
position boundary is reached.
SEQ_ALT_RST
1
0 = normal operation.
1 = automatically resets the sequence number back to the sequence defined for that particular region in the
active field register.
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參數(shù)描述
AD9920ABBCZRL 功能描述:IC PROCESSOR CCD 12BIT 105CSPBGA RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模擬前端 (AFE) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):- 通道數(shù):2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數(shù)字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:32-QFN（5x5） 包裝:帶卷 (TR)
AD9920BBCZ 制造商:Analog Devices 功能描述:
AD9920BBCZRL 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述:
AD9921BBCZ 制造商:Analog Devices 功能描述:
AD9921BBCZRL 制造商:Analog Devices 功能描述:
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