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參數(shù)資料
| 型號： | AD9920ABBCZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 37/112頁 |
| 文件大小： | 0K |
| 描述： | IC PROCESSOR CCD 12BIT 105CSPBGA |
| 標準包裝： | 1 |
| 位數(shù)： | 12 |
| 電壓 - 電源，模擬： | 1.6 V ~ 2 V |
| 電壓 - 電源，數(shù)字： | 1.6 V ~ 2 V |
| 封裝/外殼： | 105-LFBGA，CSPBGA |
| 供應商設備封裝： | 105-CSPBGA（8x8） |
| 包裝： | 管件 |
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AD9920A
Rev. B | Page 30 of 112
HBLK
H1
H2
HBLKSTART
HBLKSTARTA
HBLKEND
HBLKLEN
REPEAT AREA 0
HBLKREP = 2
TO CREATE TWO REPEAT AREAS
HD
REPEAT AREA 1
HBLKSTARTB
HBLKSTARTC
RA0H1REPA RA0H1REPB
RA0H1REPC
ALL RAxHxREPA/B/C REGISTERS = 2 TO CREATE TWO HCLK PULSES
RA1H1RE PA RA1H1REPB
RA1H1REPC
RA0H2REPA RA0H2REPB
RA0H2REPC
RA1H2REPA RA1H2REPB
RA1H2REPC
06
87
8-
03
7
Figure 38. HBLK Mode 1 Operation
As shown in Figure 38, setting the RAxH1REPA/B/C or
RAxH2REPA/B/C register to 0 masks HCLK groups from
appearing in a particular repeat area. Figure 37 shows only two
repeat areas being used, although six are available. It is possible
to program a separate number of repeat area repetitions for H1
and H2, but generally the same value is used for both H1 and
H2. Figure 37 shows an example of RA0H1REPA/B/C =
RA0H2REPA/B/C = RA1H1REPA/B/C = RA1H2REPA/B/C = 2.
Furthermore, HBLK Mode 1 allows a different HBLK pattern on
even and odd lines. The HBLKSTARTA/B/C registers, as well as
the RAxH1REPA/B/C and RAxH2REPA/B/C registers, define
operation for the even lines. For separate control of the odd lines,
the HBLKALT_PAT registers specify up to six repeat areas on
the odd lines by reordering the repeat areas used for the even
lines. New patterns are not available, but the order of the pre-
viously defined repeat areas on the even lines can be changed
for the odd lines to accommodate advanced CCD operation.
HORIZONTAL TIMING SEQUENCE EXAMPLE
Figure 39 shows an example CCD layout. The horizontal register
contains 28 dummy pixels that occur on each line clocked from
the CCD. In the vertical direction, there are 10 optical black
(OB) lines at the front of the readout and two at the back of the
readout. The horizontal direction has four OB pixels in the
front and 48 OB pixels in the back.
Figure 40 shows the basic sequence to be used during the
effective pixel readout. The 48 OB pixels at the end of each line
are used for the CLPOB signals. PBLK is optional and is often
used to blank the digital outputs during the HBLK time. HBLK
is used during the vertical shift interval.
Because PBLK is used to isolate the CDS input (see the Analog
Preblanking section), the PBLK signal should not be used
during CLPOB operation. The change in the offset behavior
that occurs during PBLK affects the accuracy of the CLPOB
circuitry.
The HBLK, CLPOB, and PBLK parameters are programmed
in the V-sequence registers. More elaborate clamping schemes,
such as adding a separate sequence to clamp in the entire shield
OB lines, can be used. This requires configuring a separate
V-sequence for clocking out the OB lines.
The CLPMASK registers are also useful for disabling the CLPOB
on a few lines without affecting the setup of the clamping
sequences. It is important that CLPOB be used only during
valid OB pixels. During other portions on the frame timing,
such as vertical blanking or SG line timing, the CCD does not
output valid OB pixels. Any CLPOB pulse that occurs during
this time causes errors in clamping operation and changes in
the black level of the image.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD9920ABBCZRL | 功能描述:IC PROCESSOR CCD 12BIT 105CSPBGA RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模擬前端 (AFE) 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數(shù):- 通道數(shù):2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數(shù)字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應商設備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
| AD9920BBCZ | 制造商:Analog Devices 功能描述: |
| AD9920BBCZRL | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| AD9921BBCZ | 制造商:Analog Devices 功能描述: |
| AD9921BBCZRL | 制造商:Analog Devices 功能描述: |
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