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參數(shù)資料
| 型號(hào)： | AD9920ABBCZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 41/112頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PROCESSOR CCD 12BIT 105CSPBGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 12 |
| 電壓 - 電源，模擬： | 1.6 V ~ 2 V |
| 電壓 - 電源，數(shù)字： | 1.6 V ~ 2 V |
| 封裝/外殼： | 105-LFBGA，CSPBGA |
| 供應(yīng)商設(shè)備封裝： | 105-CSPBGA（8x8） |
| 包裝： | 管件 |
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AD9920A
Rev. B | Page 34 of 112
VERTICAL SEQUENCES (VSEQ)
The vertical sequences are created by selecting one of the V-pattern
groups and adding repeats, start position, horizontal clamping, and
blanking information. The V-sequences are programmed using
how these registers are used to generate the V-sequences.
The VPATSELA, VPATSELB, VPATSELC, and VPATSELD
registers select which V-pattern is used in a given V-sequence.
Having four groups available allows each vertical output to be
mapped to a different V-pattern. The user can add repetitions to
the selected V-pattern group for high speed line shifts or for line
binning by using the VREP registers for odd and even lines.
Generally, the same number of repetitions is programmed into
both registers. If a different number of repetitions is required on
odd and even lines, separate values can be used for each register
section). The VSTARTA, VSTARTB, VSTARTC, and VSTARTD
registers specify where in the line the V-pattern group starts.
The VMASK_EVEN and VMASK_ODD registers are used in
conjunction with the FREEZE/RESUME registers to enable
optional masking of the V-outputs. One or more of the
FREEZE1/RESUME1, FREEZE2/RESUME2, FREEZE3/
RESUME3, and FREEZE4/RESUME4 registers can be enabled.
The line length (in pixels) is programmable using the HDLEN
registers. Each V-sequence can have a different line length to
accommodate various image readout techniques. The maximum
number of pixels per line is 8192. The last line of the field is
programmed separately using the HDLASTLEN register, which
is located in the field register section (see Table 64).
VREPA_3
HD
XV1 TO XV24
V-PATTERN GROUP
1
3
CLPOB
HBLK
2
44
VREPA_ 2
5
6
PROGRAMMABLE SETTINGS FOR EACH VERTICAL SEQUENCE:
1START POSITION IN THE LINE OF THE SELECTED V-PATTERN GROUP.
2HD LINE LENGTH.
3V-PATTERN SELECT (VPATSEL) TO SELECT ANY V-PATTERN GROUP.
4NUMBER OF REPETITIONS OF THE V-PATTERN GROUP (IF NEEDED).
5START POLARITY AND TOGGLE POSITIONS FOR CLPOB AND PBLK SIGNALS.
6MASKING POLARITY AND TOGGLE POSITIONS FOR HBLK SIGNAL.
06
87
8
-04
2
Figure 43. V-Sequence Programmability
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9920ABBCZRL | 功能描述:IC PROCESSOR CCD 12BIT 105CSPBGA RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模擬前端 (AFE) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):- 通道數(shù):2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數(shù)字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
| AD9920BBCZ | 制造商:Analog Devices 功能描述: |
| AD9920BBCZRL | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| AD9921BBCZ | 制造商:Analog Devices 功能描述: |
| AD9921BBCZRL | 制造商:Analog Devices 功能描述: |
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