- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄10753 > AD9920ABBCZ (Analog Devices Inc)IC PROCESSOR CCD 12BIT 105CSPBGA PDF資料下載
參數(shù)資料
| 型號(hào)： | AD9920ABBCZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 21/112頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PROCESSOR CCD 12BIT 105CSPBGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 12 |
| 電壓 - 電源，模擬： | 1.6 V ~ 2 V |
| 電壓 - 電源，數(shù)字： | 1.6 V ~ 2 V |
| 封裝/外殼： | 105-LFBGA，CSPBGA |
| 供應(yīng)商設(shè)備封裝： | 105-CSPBGA（8x8） |
| 包裝： | 管件 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁當(dāng)前第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁
AD9920A
Rev. B | Page 16 of 112
TERMINOLOGY
Differential Nonlinearity (DNL)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. It is often
specified in terms of resolution for which no missing codes are
guaranteed. No missing codes guaranteed to 12-bit resolution
indicates that all 4096 codes, each for its respective input, must
be present over all operating conditions.
Integral Nonlinearity (INL)
INL is defined as the maximum deviation of the actual analog
output from the ideal output, determined by a straight line
drawn from zero scale to full scale.
Peak Nonlinearity
Peak nonlinearity, a full signal chain specification, refers to the
peak deviation of the output of the AD9920A from a true straight
line. The point used as zero scale occurs 0.5 LSB before the first
code transition. Positive full scale is defined as a level 1 LSB and
0.5 LSB beyond the last code transition. The deviation is measured
from the middle of each particular output code to the true straight
line. The error is then expressed as a percentage of the 2 V ADC
full-scale signal. The input signal is always appropriately amplified
to fill the ADC full-scale range.
Power Supply Rejection (PSR)
The PSR is measured with a step change applied to the supply
pins. The PSR specification is calculated from the change in the
data outputs for a given step change in the supply voltage.
Total Output Noise
The rms output noise is measured using histogram techniques.
The standard deviation of the ADC output codes is calculated
in LSB and represents the rms noise level of the total signal
chain at the specified gain setting. The output noise can be
converted to an equivalent voltage using the relationship
1 LSB = (ADC Full Scale/2n Codes)
where n is the bit resolution of the ADC.
For the AD9920A, 1 LSB = 0.244 mV.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD73322LARUZ | IC PROCESSOR FRONTEND DL 28TSSOP |
| V300C2M50BL | CONVERTER MOD DC/DC 2V 50W |
| MAX9025EBT+T | IC COMPARATOR BTR 6-UCSP |
| AD73311LARUZ | IC PROCESSOR FRONT END LP 20SSOP |
| VE-J3F-MY-F1 | CONVERTER MOD DC/DC 72V 50W |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9920ABBCZRL | 功能描述:IC PROCESSOR CCD 12BIT 105CSPBGA RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模擬前端 (AFE) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):- 通道數(shù):2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數(shù)字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
| AD9920BBCZ | 制造商:Analog Devices 功能描述: |
| AD9920BBCZRL | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| AD9921BBCZ | 制造商:Analog Devices 功能描述: |
| AD9921BBCZRL | 制造商:Analog Devices 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。