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| 型號： | AD9920ABBCZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 42/112頁 |
| 文件大小： | 0K |
| 描述： | IC PROCESSOR CCD 12BIT 105CSPBGA |
| 標準包裝： | 1 |
| 位數(shù)： | 12 |
| 電壓 - 電源，模擬： | 1.6 V ~ 2 V |
| 電壓 - 電源，數(shù)字： | 1.6 V ~ 2 V |
| 封裝/外殼： | 105-LFBGA，CSPBGA |
| 供應商設備封裝： | 105-CSPBGA（8x8） |
| 包裝： | 管件 |
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AD9920A
Rev. B | Page 35 of 112
Table 15. Summary of V-Sequence Registers (see Table 11 and Table 12 for the CLPOB, PBLK, and HBLK Register Summary)
Register
Length
(Bits)
Description
HOLD
4
Use in conjunction with VMASK_EVEN and VMASK_ODD.
1 = Enable HOLD function instead of FREEZE/RESUME function.
CONCAT_GRP
4
Combines toggle positions of Group A, Group B, Group C, and Group D when enabled. Only Group A settings
for start, polarity, length, and repetition are used when this mode is selected.
0 = disable.
1 = enable the addition of all toggle positions from VPATSELA/B/C/D.
2 to 15 = test mode only; do not use.
VREP_MODE
2
Selects line alternation for V-output repetitions. Two separate controls: one for Group A and the other for
Group B, Group C, and Group D.
0 = disable alternation. Group A uses VREPA_1, Groups B/C/D use VREP_EVEN for all lines.
1 = two-line. Group A alternates VREPA_1 and VREPA_2. Groups B/C/D alternate VREP_EVEN and VREP_ODD.
2 = three-line. Group A alternates VREPA_1, VREPA_2, and VREPA_3. Groups B/C/D follow a VREP_EVEN,
VREP_ODD, VREP_ODD, VREP_EVEN, VREP_ODD, VREP_ODD pattern.
3 = four-line. Group A alternates VREPA_1, VREPA_2, VREPA_3, and VREPA_4. Groups B/C/D follow two-line
alternation.
LASTREPLEN_EN
4
Enable a separate pattern length to be used during the last repetition of the V-sequence. One bit for each
group (A, B, C, and D); Group A is the LSB. Set bit high to enable. Recommended value is enabled.
HDLENE
14
HD line length for even lines in the V-sequence.
HDLENO
14
HD line length for
odd lines in the V-sequence.
VPOL
24
Group A start polarity bits for each XV1 to XV24 signal.
GROUPSEL_0
24
Assigns each XV1 to XV12 signal to Group A, Group B, Group C, or Group D. Two bits for each signal.
Bits[1:0] are for XV1.
Bits[3:2] are for XV2.
Bits[23:22] are for XV12.
0 = assign to Group A.
1 = assign to Group B.
2 = assign to Group C.
3 = assign to Group D.
GROUPSEL_1
24
Assigns each XV13 to XV24 signal to Group A, Group B, Group C, or Group D. Two bits for each signal.
Bits[1:0] are for XV13.
Bits[3:2] are for XV14.
Bits[23:22] are for XV24.
0 = assign to Group A.
1 = assign to Group B.
2 = assign to Group C.
3 = assign to Group D.
VPATSELA
5
Selected V-pattern for Group A.
VPATSELB
5
Selected V-pattern for Group B.
5
Selected V-pattern for Group C.
VPATSELD
5
Selected V-pattern for Group D.
VSTARTA
13
Start position for the selected V-pattern Group A.
VSTARTB
13
Start position for the selected V-pattern Group B.
VSTARTC
13
Start position for the selected V-pattern Group C.
VSTARTD
13
Start position for the selected V-pattern Group D.
VLENA
13
Length of selected V-pattern Group A.
VLENB
13
Length of selected V-pattern Group B.
VLENC
13
Length of selected V-pattern Group C.
VLEND
13
Length of selected V-pattern Group D.
VREPA_1
13
Number of repetitions for the V-pattern Group A for first lines (even).
VREPA_2
13
Number of repetitions for the V-pattern Group A for second lines (odd).
VREPA_3
13
Number of repetitions for the V-pattern Group A for third lines.
VREPA_4
13
Number of repetitions for the V-pattern Group A for fourth lines.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9920ABBCZRL | 功能描述:IC PROCESSOR CCD 12BIT 105CSPBGA RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模擬前端 (AFE) 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數(shù):- 通道數(shù):2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數(shù)字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應商設備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
| AD9920BBCZ | 制造商:Analog Devices 功能描述: |
| AD9920BBCZRL | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| AD9921BBCZ | 制造商:Analog Devices 功能描述: |
| AD9921BBCZRL | 制造商:Analog Devices 功能描述: |
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