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參數(shù)資料
| 型號： | AD9877ABSZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 31/36頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PROCESSOR FRONT END 100MQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 12 |
| 通道數(shù)： | 3 |
| 功率（瓦特）： | 1.17W |
| 電壓 - 電源，模擬： | 3.3V |
| 電壓 - 電源，數(shù)字： | 3.3V |
| 封裝/外殼： | 100-BQFP |
| 供應(yīng)商設(shè)備封裝： | 100-MQFP（14x20） |
| 包裝： | 托盤 |
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AD9877
Rev. B | Page 4 of 36
SPECIFICATIONS
VAS = 3.3 V ± 5%, VDS = 3.3 V ± 10%, fOSCIN = 27 MHz, fSYSCLK = 216 MHz, fMCLK = 54 MHz (M = 8 and N = 4). ADC sample frequencies
derived from PLL (fMCLK), RSET = 4.02 kΩ, maximum fine gain, 75 Ω DAC load.
Table 1.
Parameter
Temp
Test
Level
Min
Typ
Max
Unit
SYSTEM CLOCK DAC SAMPLING, fSYSCLK
Frequency Range (N = 4)
Full
II
232
MHz
Frequency Range (N = 3)
Full
II
177
MHz
OSCIN and XTAL CHARACTERISTICS
Frequency Range
Full
II
3
33
MHz
Duty Cycle
25°C
II
35
50
65
%
Input Impedance
25°C
III
100||3
MΩ||pF
MCLK JITTER
Cycle to Cycle (fMCLK derived from PLL)
25°C
III
6
ps rms
Tx DAC CHARACTERISTICS
Resolution
N/A
12
Bits
Full-Scale Output Current
Full
II
4
10
20
mA
Gain Error (using internal reference)
Full
I
2.5
1
+2.5
% FS
Offset Error
25°C
I
±1.0
% FS
Reference Voltage (REFIO Level)
25°C
I
1.18
1.23
1.28
V
Differential Nonlinearity (DNL)
25°C
III
±2.5
LSB
Integral Nonlinearity (INL)
25°C
III
±8
LSB
Output Capacitance
25°C
III
5
pF
Phase Noise @ 1 kHz Offset, 42 MHz Carrier
25°C
III
110
dBc/Hz
Output Voltage Compliance Range
Full
II
0.5
+1.5
V
Wideband SFDR
5 MHz Analog Out, IOUT = 10 mA
Full
II
48
55
dBc
65 MHz Analog Out, IOUT = 10 mA
Full
II
48
51
dBc
Narrow-Band SFDR (±1 MHz Window)
65 MHz Analog Out, IOUT = 10 mA
Full
II
53
69
dBc
Tx MODULATOR CHARACTERISTICS
I/Q Offset
Full
II
50
55
dB
Pass-Band Amplitude Ripple (f < fIQCLK/8)
Full
II
±0.1
dB
Pass-Band Amplitude Ripple (f < fIQCLK/4)
Full
II
±0.5
dB
Stop-Band Response (f > fIQCLK × 3/4)
Full
II
63
dB
Tx GAIN CONTROL
Gain Step Size
25°C
III
0.5
dB
Gain Step Error
25°C
III
0.05
dB
Settling Time, 1% (Full-Scale Step)
25°C
III
1.8
μs
8-BIT ADC CHARACTERISTICS
Resolution
N/A
8
Bits
Conversion Rate
Full
II
16.5
MHz
Pipeline Delay
N/A
3.5
ADC cycles
Offset Matching Between I and Q ADCs
±8.0
LSBs
Gain Matching Between I and Q ADCs
±2.0
LSBs
Analog Input
Input Voltage Range
Full
II
1
Vppd
Differential Input Impedance
25°C
III
4||2
kΩ||pF
Full Power Bandwidth
25°C
III
90
MHz
Input Referred Noise
25°C
III
600
μV
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