- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1988 > AD9877ABSZ (Analog Devices Inc)IC PROCESSOR FRONT END 100MQFP PDF資料下載
參數(shù)資料
| 型號： | AD9877ABSZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 16/36頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PROCESSOR FRONT END 100MQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 12 |
| 通道數(shù)： | 3 |
| 功率（瓦特）： | 1.17W |
| 電壓 - 電源，模擬： | 3.3V |
| 電壓 - 電源，數(shù)字： | 3.3V |
| 封裝/外殼： | 100-BQFP |
| 供應(yīng)商設(shè)備封裝： | 100-MQFP（14x20） |
| 包裝： | 托盤 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁當(dāng)前第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁
AD9877
Rev. B | Page 23 of 36
When this bit is set default low, the AD9877 serial port is in
MSB-first format. In MSB-first mode, the instruction byte and
data bytes must be written from the MSB to the LSB. In MSB-
first mode, the serial port internal byte address generator
decrements for each byte of the multibyte communication cycle.
When incrementing from 0x1F, the address generator changes
to 0x00. When decrementing from 0x00, the address generator
changes to 0x1F.
NOTES ON SERIAL PORT OPERATION
The AD9877 serial port configuration bits reside in Bit 6 and
Bit 7 of Register 0x00. It is important to note that the
configuration changes immediately upon writing to the last bit
of the register. For multibyte transfers, writing to this register
may occur during the middle of the communication cycle.
Care must be taken to compensate for this new configuration
for the remaining bytes of the current communication cycle.
The same considerations apply to setting the RESET bit in
Register 0x00. All other registers are set to their default values,
but the software reset does not affect the bits in Register 0x00. It
is recommended to use only single-byte transfers when chang-
ing serial port configurations or initiating a software reset.
A write to Bits 1, 2, and 3 of Register 0x00 with the same logic
levels as Bits 7, 6, and 5 (bit pattern: XY1001YX binary) allows
the host processor to reprogram a lost serial port configuration
and to reset the registers to their default values. A second write
to Register 0x00 with RESET bit low and serial port configura-
tion as specified above (XY) reprograms the OSCIN multiplier
setting. A changed fSYSCLK frequency is stable after a maximum
of 200 fMCLK cycles.
CS
R/W N1
N0
A4
A3
A2
A1
A0 D7n D6n
D20 D10 D00
D7n D6n
D20 D10 D00
SCLK
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
SDIO
SDO
02716-022
Figure 22. Serial Register Interface Timing MSB First
D00 D10 D20
D6n D7n
SCLK
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
SDIO
SDO
CS
A0
A1
A2
A3
A4
N0
N1 R/W D00 D10 D20
D6n D7n
02716-023
Figure 23. Serial Register Interface Timing LSB First
02716-024
SCLK
INSTRUCTION BIT 7
INSTRUCTION BIT 6
tSCLK
tDH
tPWL
tPWH
tDS
SDIO
CS
tDS
Figure 24. Timing Diagram for Register Write to AD9877
02716-025
SCLK
SDIO
SDO
CS
DATA BIT N
DATA BIT N – 1
tDV
Figure 25. Timing Diagram for Register Read from AD9877
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD9878BSTZ | IC FRONT-END MIXED-SGNL 100-LQFP |
| AD9879BSZ | IC PROCESSOR FRONT END 100MQFP |
| AD9901KQ | IC PHASE/FREQ DISCRIMR 14-CDIP |
| AD9920ABBCZRL | IC PROCESSOR CCD 12BIT 105CSPBGA |
| AD9978BCPZRL | IC PROCESSOR CCD 14BIT 40-LFCSP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9877BS | 制造商:Analog Devices 功能描述: |
| AD9877-EB | 制造商:Analog Devices 功能描述: |
| AD9878 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Mixed-Signal Front End for Broadband Applications |
| AD9878BST | 制造商:Analog Devices 功能描述:Mixed Signal Front End 100-Pin LQFP |
| AD9878BSTRL | 制造商:Analog Devices 功能描述:Mixed Signal Front End 100-Pin LQFP T/R 制造商:Analog Devices 功能描述:MIXED SGNL FRONT END 100LQFP - Tape and Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。