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參數(shù)資料
| 型號： | AD9877ABSZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 13/36頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PROCESSOR FRONT END 100MQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 12 |
| 通道數(shù)： | 3 |
| 功率（瓦特）： | 1.17W |
| 電壓 - 電源，模擬： | 3.3V |
| 電壓 - 電源，數(shù)字： | 3.3V |
| 封裝/外殼： | 100-BQFP |
| 供應(yīng)商設(shè)備封裝： | 100-MQFP（14x20） |
| 包裝： | 托盤 |
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AD9877
Rev. B | Page 20 of 36
REGISTER 0x08—ADC CLOCK CONFIGURATION
Bit 4: Power-Down RxSYNC and 8-Bit ADC Clock
Setting this bit to 1 powers down the sampling clock of the 8-bit
ADC and stops the RxSYNC output pin. It can be used for
additional power saving on top of the power-down selections in
Register 0x02.
Bit 7: ADC Clock Select
When set high, the input clock at OSCIN is used directly as the
ADC sampling clock. When set low, the internally generated
master clock, MCLK, is used as the ADC sampling clock. Best
ADC performance is achieved when the ADCs are sampled
directly from fOSCIN using an external crystal or low jitter crystal
oscillator.
REGISTER 0x0C—DIE REVISION
Bits 0–3: Version
The die version of the chip can be read from this register.
REGISTER 0x0D—Tx FREQUENCY TUNING WORDS
LSBs
This register accommodates 2 LSBs for each of the four
frequency tuning words (see the Registers 0X10–0X1F—Burst
Parameter section).
REGISTER 0x0E—DAC GAIN CONTROL
This register allows the user to program the DAC gain if Tx
Gain Control Select Bit 3 in Register 0x0F is set to 0.
Table 6. DAC Gain Control
Bits [3:0]
DAC Gain
0000
0.0 dB (default)
0001
0.5 dB
0010
1.0 dB
0011
1.5 dB
...
1110
7.0 dB
1111
7.5 dB
REGISTER 0x0F—Tx PATH CONFIGURATION
Bit 0: Single-Tone Tx Mode
Active high configures the AD9877 for single-tone applications
such as FSK. The AD9877 will supply a single-frequency output
as determined by the frequency tuning word selected by the
active profile. In this mode, the TxIQ input data pins are
ignored but should be tied to a valid logic voltage level. Default
value is 0 (inactive).
Bit 1: Spectral Inversion Tx
When set to 1, inverted modulation is performed.
MODULATOR_OUT = [I cos(ωt) + Q sin(ωt)]
Default is logic low, noninverted modulation.
MODULATOR_OUT = [I cos(ωt) Q sin(ωt)]
Bit 3: CA Interface Mode Select
This bit changes the manner in which transmit gain control is
performed. Typically, either AD8321/AD8325 (Default 0) or
AD8322/AD8327 (Default 1) variable gain cable amplifiers are
programmed over the chip’s 3-wire cable amplifier (CA)
interface. The Tx gain control select changes the interpretation
of the bits in Registers 0x13, 0x17, 0x1B, and 0x1F (see the
Cable Driver Gain Control section).
Bits 4–5: Profile Select
The AD9877 quadrature digital upconverter is capable of
storing four preconfigured modulation modes called profiles.
Each profile defines a transmit frequency tuning word and cable
driver amplifier gain (DAC gain) setting. Profile Select [1:0] bits
or PROFILE [1:0] pins program the current register profile to
be used. Profile Select bits should always be 0 if PROFILE[1:0]
pins are used to switch between profiles. Using the Profile Select
bits as a means of switching between different profiles requires
the PROFILE [1:0] pins to be tied low.
REGISTERS 0x10–0x1F—BURST PARAMETER
Tx Frequency Tuning Words
The frequency tuning word (FTW) determines the DDS-
generated carrier frequency (fC) and is formed via a
concatenation of register addresses.
The 26-bit FTW is spread over four register addresses. Bit 25 is
the MSB, and Bit 0 is the LSB.
The carrier frequency equation is given as
fc = [FTW × fSYSCLK]/226
where:
fSYSCLK = M × fOSCIN.
FTW < 0 × 2000000.
Changes to FTW bytes take effect immediately.
Cable Driver Gain Control
The AD9877 has a three-pin interface to the AD832x family of
programmable gain cable driver amplifiers. This allows direct
control of the cable driver’s gain through the AD9877.
In its default mode, the complete 8-bit register value is
transmitted over the 3-wire CA interface.
If Bit 3 of Register 0x0F is set high, Bits [7:4] determine the
8-bit word sent over the CA interface according to Table 7.
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