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參數(shù)資料
| 型號： | AD9877ABSZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 20/36頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PROCESSOR FRONT END 100MQFP |
| 標準包裝： | 1 |
| 位數(shù)： | 12 |
| 通道數(shù)： | 3 |
| 功率（瓦特）： | 1.17W |
| 電壓 - 電源，模擬： | 3.3V |
| 電壓 - 電源，數(shù)字： | 3.3V |
| 封裝/外殼： | 100-BQFP |
| 供應(yīng)商設(shè)備封裝： | 100-MQFP（14x20） |
| 包裝： | 托盤 |
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AD9877
Rev. B | Page 27 of 36
Q
XZ
X
I
02716-035
Figure 35. 16-Quadrature Modulation
Tx SIGNAL LEVEL CONSIDERATIONS
The quadrature modulator introduces a maximum gain of 3 dB
in the signal level. To visualize this, assume that both the I data
and Q data are fixed at the maximum possible digital value, x.
Then the output of the modulator, z, is
z = [x cos(ωt) x sin(ωt)]
It can be shown that |z| assumes a maximum value of
()
dB
3
2
+
=
+
=
of
gain
a
x
z
However, if the same number of bits are used to represent the |z|
values as is used to represent the x values, an overflow occurs.
To prevent this possibility, an effective 3 dB attenuation is
internally implemented on the I and Q data path.
()
(
)
x
z
=
+
=
2
/
1
2
/
1
The following example assumes a Pk/rms level of 10 dB:
Maximum Symbol Component Input Value =
±(2,047 LSBs 0.2 dB) = ±2,000 LSBs
Maximum Complex Input RMS Value =
2,000 LSBs + 6 dB Pk/rms (dB) = 1,265 LSBs rms
Maximum complex input rms value calculation uses both I and
Q symbol components, which adds a factor of 2 (6 dB) to the
formula.
Table 11 shows typical IQ input test signals with amplitude
levels related to 12-bit full scale (FS).
ATTENUATOR
–3dB
MODULATOR
≤3dB MAX
I
OO
I
ATTENUATOR
–3dB
TWOS COMPLEMENT FORMAT
HBF + CIC
INTERPOLATOR
+0.2dB
HBF + CIC
INTERPOLATOR
+0.2dB
12
I
O
COMPLEX DATA INPUT
DAC
02716-036
Figure 36. Signal Level Contribution
Tx THROUGHPUT AND LATENCY
Data inputs impact the output fairly quickly but remain
effective due to the filter characteristics of the AD9877. Data
transmit latency through the AD9877 is easiest to describe in
terms of fSYSCLK clock cycles (4 fMCLK). The numbers quoted are
when an effect is first seen after an input value changes.
Latency of I/Q data entering the data assembler (AD9877 input)
to the DAC output is 119 fSYSCLK clock cycles (29.75 fMCLK cycles).
DC values applied to the data assembler input take up to 176
fSYSCLK clock cycles (44 fMCLK cycles) to propagate and settle at the
DAC output.
Frequency hopping is accomplished via changing the PROFILE
input pins. The time required to switch from one frequency to
another is less than 232 fSYSCLK cycles (58.5 fMCLK cycles).
DIGITAL-TO-ANALOG CONVERTER
A 12-bit digital-to-analog converter (DAC) is used to convert
the digitally processed waveform into an analog signal. The
worst-case spurious signals due to the DAC are the harmonics
of the fundamental signal and their aliases. The conversion
process produces aliased components of the fundamental signal
at n × fSYSCLK ± fCARRIER (n = 1, 2, and 3). These are typically
filtered with an external RLC filter at the DAC output.
It is important for this analog filter to have a sufficiently flat
gain and linear phase response across the bandwidth of interest
to avoid modulation impairments. A relatively inexpensive
seventh-order elliptical low-pass filter is sufficient to suppress
the aliased components for HFC network applications.
Table 11. IQ Input Test Signals
Analog Output
Digital Input
Input Level
Modulator Output Level
Single Tone (fC f)
I = cos(f)
FS 0.2 dB
FS 3.0 dB
Q = cos(f + 90°) = sin(f)
FS 0.2 dB
Single Tone (fC + f)
I = cos(f)
FS 0.2 dB
FS 3.0 dB
Q = cos(f + 270°) = +sin(f)
FS 0.2 dB
Dual Tone (fC ± f)
I = cos(f)
FS 0.2 dB
FS
Q = cos(f + 180°) = cos(f) or Q = +cos(f)
FS 0.2 dB
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