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參數(shù)資料
| 型號： | AD9877ABSZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 24/36頁 |
| 文件大小： | 0K |
| 描述： | IC PROCESSOR FRONT END 100MQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 12 |
| 通道數(shù)： | 3 |
| 功率（瓦特）： | 1.17W |
| 電壓 - 電源，模擬： | 3.3V |
| 電壓 - 電源，數(shù)字： | 3.3V |
| 封裝/外殼： | 100-BQFP |
| 供應(yīng)商設(shè)備封裝： | 100-MQFP（14x20） |
| 包裝： | 托盤 |
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AD9877
Rev. B | Page 30 of 36
RECEIVE PATH (Rx)
ADC THEORY OF OPERATION
The analog-to-digital converters of the AD9877 implement
pipelined multistage architectures to achieve high sample rates
while consuming low power. Each ADC distributes the
conversion over several smaller ADC subblocks, refining the
conversion with progressively higher accuracy as it passes the
results from stage to stage.
As a consequence of the distributed conversion, ADCs require a
small fraction of the 2n comparators used in a traditional n-bit
flash-type ADC. A sample-and-hold function within each of the
stages permits the first stage to operate on a new input sample
while the remaining stages operate on preceding samples. Each
stage of the pipeline, excluding the last, consists of a low
resolution flash ADC connected to a switched capacitor DAC
and interstage residue amplifier (MDAC). The residue amplifier
amplifies the difference between the reconstructed DAC output
and the flash input for the next stage in the pipeline. One bit of
redundancy is used in each stage to facilitate digital correction
of flash errors. The last stage simply consists of a flash ADC.
The analog inputs of the AD9877 incorporate a novel structure
that merges the input sample-and-hold amplifiers (SHA) and
the first pipeline residue amplifiers into single, compact
switched capacitor circuits. This structure achieves considerable
noise and power savings over a conventional implementation
that uses separate amplifiers by eliminating one amplifier in the
pipeline. By matching the sampling network of the input SHA
with the first stage flash ADC, the ADCs can sample inputs well
beyond the Nyquist frequency with no degradation in
performance.
The digital data outputs of the ADCs are represented in straight
binary format. They saturate to full scale or zero scale when the
input signal exceeds the input voltage range.
RECEIVE TIMING
The AD9877 sends multiplexed data to the RxIQ outputs upon
every rising edge of MCLK. The data stream consists of two
nibbles of I data followed by two nibbles of Q data. The
RxSYNC pulse frames the I/Q data and is coincidentally high
with the most significant nibble of the I data-word. If the 8-bit
I/Q ADC is in power-down mode, the RxSYNC signal will not
be generated.
The 12-bit ADC data is sent to the IF[11:0] outputs upon every
second falling edge of MCLK.
In its default setting, the REFCLK pin provides a buffered
version of fOSCIN. REFCLK can be used as a qualifying clock for
the Rx data when the ratio between the OSCIN multiplier and
the OSCIN divider is programmed to be 2 (M/N = 2) or when
the ADC sampling is selected to be derived from fOSCIN directly.
DRIVING THE ANALOG INPUTS
Figure 40 illustrates the equivalent analog inputs of the AD9877
(a switched capacitor input). Bringing CLK to a logic high
opens Switch S3 and closes Switches S1 and S2. The input
source is connected to AIN and must charge capacitor CH
during this time. Bringing CLK to a logic low opens switch S2,
and then Switch S1 opens followed by closing switch S3. This
places the input into hold mode.
The structure of the input SHA places certain requirements on
the input drive source. The combination of the pin capacitance
and the hold capacitance of CH is typically less than 5 pF. The
input source must be able to charge or discharge this
capacitance to its n-bit accuracy in one-half of a clock cycle.
When the SHA goes into track mode, the input source must
charge or discharge capacitor CH from the voltage already stored
on CH to the new voltage. In the worst case, a full-scale voltage
step on the input source must provide the charging current
through the RON (100 Ω) of Switch S1 and quickly (within
1/2 CLK period) settle. This situation corresponds to driving a
low input impedance.
D/A
A/D
SHA
CORRECTION LOGIC
D/A
A/D
SHA
GAIN
AINP
AINN
AD9877
02716-
039
Figure 39. ADC Architecture
AINP
AINN
2k
Ω
2k
Ω
VBIAS
S1
S3
CP
CH
S2
AD9877
02716-040
Figure 40. Differential Input Architecture
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