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參數(shù)資料
| 型號(hào)： | AD9877ABSZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 22/36頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PROCESSOR FRONT END 100MQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 12 |
| 通道數(shù)： | 3 |
| 功率（瓦特）： | 1.17W |
| 電壓 - 電源，模擬： | 3.3V |
| 電壓 - 電源，數(shù)字： | 3.3V |
| 封裝/外殼： | 100-BQFP |
| 供應(yīng)商設(shè)備封裝： | 100-MQFP（14x20） |
| 包裝： | 托盤 |
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AD9877
Rev. B | Page 29 of 36
PROGRAMMING THE AD8321/AD8325 OR AD8322/AD8327 CABLE DRIVER AMPLIFIER
GAIN CONTROL
Programming the gain of the AD832x family cable driver
amplifier can be accomplished via the AD9877 cable amplifier
control interface. Four 8-bit registers within the AD9877 (one
per profile) store the gain value to be written to the serial 3-wire
port. Typically either AD8321/AD8325 or AD8322/AD8327
variable gain cable amplifiers are connected to the chip’s 3-wire
cable amplifier interface. The Tx gain control select bit in
Register 0x0F changes the interpretation of the bits in Registers
0x13, 0x17, 0x1B, and 0x1F. See the Cable Driver Gain Control
section register description.
Data transfers to the gain programmable cable driver amplifier
are initiated by the following four conditions.
1.
Power-Up and Hardware Reset—Upon initial power-up
and every hardware reset, the AD9877 clears the contents
of the gain control registers to 0, which defines the lowest
gain setting of the AD832x. Thus, the AD9877 writes all 0s
out of the 3-wire cable amplifier control interface.
2.
Software Reset—Writing a 1 to Bit 5 of Address 0x00
initiates a software reset. Upon a software reset, the
AD9877 clears the contents of the gain control registers to
0 for the lowest gain and sets the profile select to 0. The
AD9877 writes all 0s out of the 3-wire cable amplifier
control interface if the gain was previously on a different
setting (other than 0).
3.
Change in Profile Selection—The AD9877 samples the
PROFILE(1) and PROFILE(2) input pins together with the
two profile select bits and writes to the AD832x gain
control registers if a change in profile and gain is
determined. The data written to the cable driver amplifier
comes from the AD9877 gain control register associated
with the current profile.
4.
Write to AD9877 Cable Driver Amplifier Control
Registers—The AD9877 will write gain control data
associated with the current profile to the AD832x
whenever the selected AD9877 cable driver amplifier gain
setting is changed.
Once a new stable gain value has been detected (48 MCLK to
64 MCLK cycles after initiation), a data write starts with CA_CS
going low. The AD9877 always finishes a write sequence to the
cable driver amplifier once it is started. The logic controlling
data transfers to the cable driver amplifier uses up to 200 MCLK
cycles and is designed to prevent erroneous write cycles from
occurring.
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