參數(shù)資料
型號(hào): AD9653BCPZRL7-125
廠商: Analog Devices Inc
文件頁(yè)數(shù): 39/40頁(yè)
文件大?。?/td> 0K
描述: IC ADC 16BIT 125MSPS SRL 48LFCSP
標(biāo)準(zhǔn)包裝: 750
位數(shù): 16
采樣率(每秒): 125M
數(shù)據(jù)接口: LVDS,串行,SPI?
轉(zhuǎn)換器數(shù)目: 4
功率耗散(最大): 708mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-WFQFN 裸露焊盤(pán),CSP
供應(yīng)商設(shè)備封裝: 48-LFCSP-WQ(7x7)
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 4 個(gè)差分,單極
AD9653
Data Sheet
Rev. 0 | Page 8 of 40
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, unless otherwise noted.
Table 6.
Parameter1, 2
Temp
Min
Typ
Max
Unit
CLOCK3
Input Clock Rate
Full
20
1000
MHz
Conversion Rate
Full
20
125
MSPS
Clock Pulse Width High (t
EH)
Full
4.00
ns
Clock Pulse Width Low (t
EL)
Full
4.00
ns
OUTPUT PARAMETERS3
Propagation Delay (t
PD)
Full
2.3
ns
Rise Time (t
R) (20% to 80%)
Full
300
ps
Fall Time (t
F) (20% to 80%)
Full
300
ps
FCO Propagation Delay (t
FCO)
Full
1.5
2.3
3.1
ns
DCO Propagation Delay (t
CPD)
Full
t
FCO + (tSAMPLE/16)
ns
DCO to Data Delay (t
DATA)
Full
(t
SAMPLE/16) 300
(t
SAMPLE/16)
(t
SAMPLE/16) + 300
ps
DCO to FCO Delay (t
FRAME)
Full
(t
SAMPLE/16) 300
(t
SAMPLE/16)
(t
SAMPLE/16) + 300
ps
Lane Delay (t
LD)
90
ps
Data to Data Skew (t
DATA-MAX tDATA-MIN)
Full
±50
±200
ps
Wake-Up Time (Standby)
25°C
250
ns
Wake-Up Time (Power-Down)5
25°C
375
μs
Pipeline Latency
Full
16
Clock cycles
APERTURE
Aperture Delay (t
A)
25°C
1
ns
Aperture Uncertainty (Jitter, t
J)
25°C
135
fs rms
Out-of-Range Recovery Time
25°C
1
Clock cycles
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.
2 Measured on standard FR-4 material.
3 Can be adjusted via the SPI. The conversion rate is the clock rate after the divider.
4 t
SAMPLE/16 is based on the number of bits in two LVDS data lanes. tSAMPLE = 1/fS.
5 Wake-up time is defined as the time required to return to normal operation from power-down mode.
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