Figure 60. Typical VREF = 1.0 V Drift <" />
參數(shù)資料
型號(hào)： AD9653BCPZRL7-125
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 18/40頁(yè)
文件大?。?/td> 0K
描述： IC ADC 16BIT 125MSPS SRL 48LFCSP
標(biāo)準(zhǔn)包裝： 750
位數(shù)： 16
采樣率（每秒）： 125M
數(shù)據(jù)接口： LVDS，串行，SPI?
轉(zhuǎn)換器數(shù)目： 4
功率耗散（最大）： 708mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 48-WFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 48-LFCSP-WQ（7x7）
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 4 個(gè)差分，單極
Data Sheet
AD9653
Rev. 0 | Page 25 of 40
Figure 60. Typical VREF = 1.0 V Drift
Figure 61. Typical VREF = 1.3 V Drift
When the SENSE pin is tied to AVDD, the internal reference is
disabled, allowing the use of an external reference. An internal
reference buffer loads the external reference with an equivalent
7.5 k load (see Figure 50). The internal buffer generates the
positive and negative full-scale references for the ADC core.
It is not recommended to leave the SENSE pin floating.
CLOCK INPUT CONSIDERATIONS
For optimum performance, clock the AD9653 sample clock
inputs, CLK+ and CLK, with a differential signal. The signal
is typically ac-coupled into the CLK+ and CLK pins via a
transformer or capacitors. These pins are biased internally
(see Figure 44) and require no external bias.
Clock Input Options
The AD9653 has a flexible clock input structure. The clock input
can be a CMOS, LVDS, LVPECL, or sine wave signal. Regard-
less of the type of signal being used, clock source jitter is of the
most concern, as described in the Jitter Considerations section.
Figure 62 and Figure 63 show two preferred methods for clock-
ing the AD9653 (at clock rates up to 1 GHz prior to internal clock
divider). A low jitter clock source is converted from a single-
ended signal to a differential signal using either an RF transformer
or an RF balun.
The RF balun configuration is recommended for clock frequencies
between 125 MHz and 1 GHz, and the RF transformer is recom-
mended for clock frequencies from 20 MHz to 200 MHz. The
back-to-back Schottky diodes across the transformer/balun
secondary winding limit clock excursions into the AD9653 to
approximately 0.8 V p-p differential.
This limit helps prevent the large voltage swings of the clock
from feeding through to other portions of the AD9653 while
preserving the fast rise and fall times of the signal that are critical
to achieving low jitter performance. However, the diode capaci-
tance comes into play at frequencies above 500 MHz. Care must be
taken in choosing the appropriate signal limiting diode.
Figure 62. Transformer-Coupled Differential Clock (Up to 200 MHz)
Figure 63. Balun-Coupled Differential Clock (Up to 1 GHz)
If a low jitter clock source is not available, another option is to
ac couple a differential PECL signal to the sample clock input
pins, as shown in Figure 64. The AD9510/AD9511/AD9512/
excellent jitter performance.
A third option is to ac couple a differential LVDS signal to the
sample clock input pins, as shown in Figure 65. The AD9510/
clock drivers offer excellent jitter performance.
In some applications, it may be acceptable to drive the sample
clock inputs with a single-ended 1.8 V CMOS signal. In such
applications, drive the CLK+ pin directly from a CMOS gate, and
bypass the CLK pin to ground with a 0.1 μF capacitor (see
Figure 64. Differential PECL Sample Clock (Up to 1 GHz)
4
–8
–40
85
V
RE
F
E
RRO
R
(
mV
)
TEMPERATURE (°C)
–6
–4
–2
0
2
–15
10
35
60
10538-
060
–15
–10
–5
0
5
10
–40
–20
0
20
40
60
80
V
RE
F
E
RRO
R
(
mV
)
TEMPERATURE (°C)
10538-
061
0.1F
SCHOTTKY
DIODES:
HSMS2822
CLOCK
INPUT
50
100
CLK–
CLK+
ADC
Mini-Circuits
ADT1-1WT, 1:1 Z
XFMR
10538-
062
0.1F
CLOCK
INPUT
0.1F
50
CLK–
CLK+
SCHOTTKY
DIODES:
HSMS2822
ADC
10538-
063
10
0
0.1F
240
50k
CLK–
CLK+
CLOCK
INPUT
CLOCK
INPUT
ADC
AD951x
PECL DRIVER
10538-
064
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