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參數(shù)資料
| 型號： | AD9653BCPZRL7-125 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 31/40頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 16BIT 125MSPS SRL 48LFCSP |
| 標(biāo)準(zhǔn)包裝： | 750 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 125M |
| 數(shù)據(jù)接口： | LVDS，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 4 |
| 功率耗散（最大）： | 708mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-WFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 48-LFCSP-WQ（7x7） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 4 個差分，單極 |
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Data Sheet
AD9653
Rev. 0 | Page 37 of 40
MEMORY MAP REGISTER DESCRIPTIONS
For additional information about functions controlled in
Register 0x00 to Register 0xFF, see the AN-877 Application Note,
Interfacing to High Speed ADCs via SPI.
Device Index (Register 0x05)
There are certain features in the map that can be set inde-
pendently for each channel, whereas other features apply
globally to all channels (depending on context) regardless of
which are selected. The first four bits in Register 0x05 can be
used to select which individual data channels are affected. The
output clock channels can be selected in Register 0x05 as well.
A smaller subset of the independent feature list can be applied
to those devices.
Transfer (Register 0xFF)
All registers except Register 0x100 are updated the moment
they are written. Setting Bit 0 of this transfer register high
initializes the settings in the sample rate override register
(Address 0x100).
Power Modes (Register 0x08)
Bits[7:6]—Open
Bit 5—External Power-Down Pin Function
If set, the external PDWN pin initiates standby mode. If cleared,
the external PDWN pin initiates power-down mode.
Bits[4:2]—Open
Bits[1:0]—Power Mode
In normal operation (Bits[1:0] = 00), all ADC channels are
active.
In power-down mode (Bits[1:0] = 01), the digital datapath clocks
are disabled while the digital datapath is reset. Outputs are
disabled.
In standby mode (Bits[1:0] = 10), the digital datapath clocks
and the outputs are disabled.
During a digital reset (Bits[1:0] = 11), all the digital datapath
clocks and the outputs (where applicable) on the chip are reset,
except the SPI port. Note that the SPI is always left under
control of the user; that is, it is never automatically disabled or
in reset (except by power-on reset).
Clock (Register 0x09)
Bits[7:1]—Open
Bit 0—Duty Cycle Stabilize.
The default state is Bit 0 = 1, duty cycle stabilizer off.
Note that, when the part is not in SPI mode, the duty cycle
stabilizer is on. Refer to the Configuration Without the SPI
section for more information.
Enhancement Control (Register 0x0C)
Bits[7:3]—Open
Bit 2—Chop Mode
For applications that are sensitive to offset voltages and other
low frequency noise, such as homodyne or direct conversion
receivers, chopping in the first stage of the AD9653 is a feature
that can be enabled by setting Bit 2. In the frequency domain,
chopping translates offsets and other low frequency noise to
fCLK/2 where it can be filtered.
Bits[1:0]—Open
Output Mode (Register 0x14)
Bit 7—Open
Bit 6—LVDS-ANSI/LVDS-IEEE Option
Setting this bit chooses LVDS-IEEE (reduced range) option.
The default setting is LVDS-ANSI. As described in Table 20,
when LVDS-ANSI or LVDS-IEEE reduced range link is selected,
the user can select the driver termination. The driver current
is automatically selected to give the proper output swing.
Table 20. LVDS-ANSI/LVDS-IEEE Options
Output
Mode,
Bit 6
Output
Mode
Output
Driver
Termination
Output Driver
Current
0
LVDS-ANSI
User
selectable
Automatically
selected to give
proper swing
1
LVDS-IEEE
reduced
range link
User
selectable
Automatically
selected to give
proper swing
Bits[5:3]—Open
Bit 2—Output Invert
Setting this bit inverts the output bit stream.
Bit 1—Open
Bit 0—Output Format
By default, this bit is set to send the data output in twos
complement format. Resetting this bit changes the output mode
to offset binary.
Output Adjust (Register 0x15)
Bits[7:6]—Open
Bits[5:4]—Output Driver Termination
These bits allow the user to select the internal termination
resistor.
Bits[3:1]—Open
Bit 0—Output Drive
Bit 0 of the output adjust register controls the drive strength on
the LVDS driver of the FCO and DCO outputs only. The default
values set the drive to 1× while the drive can be increased to 2×
by setting the appropriate channel bit in Register 0x05 and then
setting Bit 0. These features cannot be used with the output
driver termination select. The termination selection takes
precedence over the 2× driver strength on FCO and DCO when
both the output driver termination and output drive are selected.
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