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參數(shù)資料
| 型號： | AD9653BCPZRL7-125 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 15/40頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 16BIT 125MSPS SRL 48LFCSP |
| 標準包裝： | 750 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 125M |
| 數(shù)據(jù)接口： | LVDS，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 4 |
| 功率耗散（最大）： | 708mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-WFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 48-LFCSP-WQ（7x7） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 4 個差分，單極 |
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AD9653
Data Sheet
Rev. 0 | Page 22 of 40
THEORY OF OPERATION
The AD9653 is a multistage, pipelined ADC. Each stage
provides sufficient overlap to correct for flash errors in the
preceding stage. The quantized outputs from each stage are
combined into a final 16-bit result in the digital correction
logic. The serializer transmits this converted data in a 16-bit
output. The pipelined architecture permits the first stage to
operate with a new input sample while the remaining stages
operate with preceding samples. Sampling occurs on the rising
edge of the clock.
Each stage of the pipeline, excluding the last, consists of a low
resolution flash ADC connected to a switched-capacitor DAC
and an interstage residue amplifier (for example, a multiplying
digital-to-analog converter (MDAC)). The residue amplifier
magnifies the difference between the reconstructed DAC output
and the flash input for the next stage in the pipeline. One bit of
redundancy is used in each stage to facilitate digital correction
of flash errors. The last stage simply consists of a flash ADC.
The output staging block aligns the data, corrects errors, and
passes the data to the output buffers. The data is then serialized
and aligned to the frame and data clocks.
ANALOG INPUT CONSIDERATIONS
The analog input to the AD9653 is a differential switched-
capacitor circuit designed for processing differential input
signals. This circuit can support a wide common-mode range
while maintaining excellent performance. By using an input
common-mode voltage of midsupply, users can minimize
signal-dependent errors and achieve optimum performance.
Figure 51. Switched-Capacitor Input Circuit
The clock signal alternately switches the input circuit between
sample mode and hold mode (see Figure 51). When the input
circuit is switched to sample mode, the signal source must be
capable of charging the sample capacitors and settling within
one-half of a clock cycle. A small resistor in series with each
input can help reduce the peak transient current injected from
the output stage of the driving source. In addition, low Q inductors
or ferrite beads can be placed on each leg of the input to reduce
high differential capacitance at the analog inputs and therefore
achieve the maximum bandwidth of the ADC. Such use of low
Q inductors or ferrite beads is required when driving the converter
front end at high IF frequencies. Either a differential capacitor or
two single-ended capacitors can be placed on the inputs to
provide a matching passive network. This ultimately creates a
low-pass filter at the input to limit unwanted broadband noise.
and the Analog Dialogue article “Transformer-Coupled Front-
End for Wideband A/D Converters” (Volume 39, April 2005) for
more information. In general, the precise values depend on the
application.
Input Common Mode
The analog inputs of the AD9653 are not internally dc-biased.
Therefore, in ac-coupled applications, the user must provide
this bias externally. Setting the device so that VCM = AVDD/2 is
recommended for optimum performance, but the device can
function over a wider range with reasonable performance, as
shown in Figure 52 and Figure 53.
An on-chip, common-mode voltage reference is included in the
design and is available from the VCM pin. The VCM pin must
be bypassed to ground by a 0.1 F capacitor, as described in the
Applications Information section.
Maximum SNR performance is achieved by setting the ADC to
the largest span in a differential configuration. In the case of the
AD9653, the input span is dependent on the reference voltage
(see Table 11).
Figure 52. SNR/SFDR vs. Common-Mode Voltage,
fIN = 9.7 MHz, fSAMPLE = 125 MSPS, VREF = 1.0 V
S
H
CPAR
CSAMPLE
CPAR
VIN–x
H
S
H
VIN+x
H
10538-
051
20
30
40
50
60
70
80
90
100
110
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
S
NR/
S
F
DR
(
d
BF
S
/d
Bc)
COMMON-MODE VOLTAGE (V)
SFDR (dBc)
SNRFS (dBFS)
10538-
052
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