參數(shù)資料
型號(hào)： AD9548/PCBZ
廠(chǎng)商： Analog Devices Inc
文件頁(yè)數(shù)： 86/112頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL FOR AD9548
產(chǎn)品變化通告： AD9548 Mask Change 20/Oct/2010
設(shè)計(jì)資源： AD9548 Schematic
AD9548 BOM
AD9548 Eval Brd Layers
標(biāo)準(zhǔn)包裝： 1
主要目的： 計(jì)時(shí)，時(shí)鐘發(fā)生器
嵌入式： 否
已用 IC / 零件： AD9548
主要屬性： 62.5 ~ 450 MHz 輸出頻率
次要屬性： SPI 和 I2C 兼容控制端口
已供物品： 板
Data Sheet
AD9548
Rev. E | Page 75 of 112
DPLL CONFIGURATION (REGISTER 0x0300 TO REGISTER 0x031B)
Table 57. Free Running Frequency Tuning Word1
Address
Bits
Bit Name
Description
0x0300
[7:0]
Frequency
(expressed as a 48-bit
frequency tuning
word)
Free running frequency tuning word, Bits[7:0]
0x0301
[7:0]
Free running frequency tuning word, Bits[15:8]
0x0302
[7:0]
Free running frequency tuning word, Bits[23:9]
0x0303
[7:0]
Free running frequency tuning word, Bits[31:24]
0x0304
[7:0]
Free running frequency tuning word, Bits[39:32]
0x0305
[7:0]
Free running frequency tuning word, Bits[47:40]
1
The default free running tuning word is 0x000000 = 0, which equates to 0 Hz.
Table 58. Update TW
Address
Bits
Bit Name
Description
0x0306
[7:1]
Unused
[0]
Update TW
A Logic 1 written to this bit transfers the free running frequency tuning word
(Register 0300 to Register 0305) to the register imbedded in the tuning word
processing logic. Note that it is not necessary to write the update TW bit when the
device is in free-run mode. This is an autoclearing bit.
Table 59. Pull-In Range Lower Limit1
Address
Bits
Bit Name
Description
0x0307
[7:0]
Pull-in range lower
limit (expressed as a
24-bit frequency
tuning word)
Lower limit pull-in range, Bits[7:0]
0x0308
[7:0]
Lower limit pull-in range, Bits[15:8]
0x0309
[7:0]
Lower limit pull-in range, Bits[23:9]
0x030A
[7:0]
Pull-in range upper
limit (expressed as a
24-bit frequency
tuning word)
Upper limit pull-in range, Bits[7:0]
0x030B
[7:0]
Upper limit pull-in range, Bits[15:8]
0x030C
[7:0]
Upper limit pull-in range, Bits[23:9]
1
The default pull-in range lower limit is 0 and the upper range limit is 0xFFFFFF, which effectively spans the full output frequency range of the DDS.
Table 60. DDS Phase Offset1
Address
Bits
Bit Name
Description
0x030D
[7:0]
Open-loop phase
offset (expressed in
π/215 radians)
DDS phase offset, Bits[7:0]
0x030E
[7:0]
DDS phase offset, Bits[15:8]
1
The default DDS phase offset is 0.
Table 61. Fixed Closed-Loop Phase Lock Offset1
Address
Bits
Bit Name
Description
0x030F
[7:0]
Fixed phase lock
offset (expressed in
pico-seconds)
Fixed phase lock offset, Bits[7:0]
0x0310
[7:0]
Fixed phase lock offset, Bits[15:8]
0x0311
[7:0]
Fixed phase lock offset, Bits[23:16]
0x0312
[7:0]
Fixed phase lock offset, Bits[31:24]
0x0313
[7:0]
Fixed phase lock offset, Bits[39:32]
1
The default fixed closed loop phase lock offset is 0.
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