參數(shù)資料
型號： AD9548/PCBZ
廠商： Analog Devices Inc
文件頁數(shù)： 52/112頁
文件大?。?/td> 0K
描述： BOARD EVAL FOR AD9548
產(chǎn)品變化通告： AD9548 Mask Change 20/Oct/2010
設(shè)計資源： AD9548 Schematic
AD9548 BOM
AD9548 Eval Brd Layers
標準包裝： 1
主要目的： 計時，時鐘發(fā)生器
嵌入式： 否
已用 IC / 零件： AD9548
主要屬性： 62.5 ~ 450 MHz 輸出頻率
次要屬性： SPI 和 I2C 兼容控制端口
已供物品： 板
AD9548
Data Sheet
Rev. E | Page 44 of 112
STATUS AND CONTROL
MULTIFUNCTION PINS (M0 TO M7)
The AD9548 has eight digital CMOS I/O pins (M0 to M7) that
are configurable for a variety of uses. The function of these pins
is programmable via the register map. Each pin can control or
monitor an assortment of internal functions based on the contents
of Register 0x0200 to Register 0x0207. To monitor an internal
function with a multifunction pin, write a Logic 1 to the most
significant bit of the register associated with the desired
multifunction pin. The value of the seven least significant bits of
the register defines the control function, as shown in Table 25.
Table 25. Multifunction Pin Output Functions, Register 0x0200
to Register 0x0207 (Bit 7 = 1)
Bits[6:0]
Value
Output Function
Source Proxy
0
Static Logic 0
1
Static Logic 1
2
System clock divided
by 32
3
Watchdog timer
output
4
EEPROM upload in
progress
Register 0x0D00, Bit 0
5
EEPROM download in
progress
Register 0x0D00, Bit 1
6
EEPROM fault detected
Register 0x0D00, Bit 2
7
SYSCLK PLL lock
detected
Register 0x0D01, Bit 0
8
SYSCLK PLL calibration
in progress
Register 0x0D01, Bit 1
9
Unused
10
Unused
11
SYSCLK PLL stable
Register 0x0D01, Bit 4
12 to 15
Unused
16
DPLL free running
Register 0x0D0A, Bit 0
17
DPLL active
Register 0x0D0A, Bit 1
18
DPLL in holdover
Register 0x0D0A, Bit 2
19
DPLL in reference
switchover
Register 0x0D0A, Bit 3
20
Active reference: phase
master
Register 0x0D0A, Bit 6
21
DPLL phase locked
Register 0x0D0A, Bit 4
22
DPLL frequency locked
Register 0x0D0A, Bit 5
23
DPLL phase slew
limited
Register 0x0D0A, Bit 7
24
DPLL frequency
clamped
Register 0x0D0B, Bit 7
25
Tuning word history
available
Register 0x0D0B, Bit 6
26
Tuning word history
updated
Register 0x0D05, Bit 4
27 to 31
Unused
32
Reference A fault
Register 0x0D0C, Bit 2
33
Reference AA fault
Register 0x0D0D, Bit 2
34
Reference B fault
Register0x0D0E, Bit 2
Bits[6:0]
Value
Output Function
Source Proxy
35
Reference BB fault
Register 0x0D0F, Bit 2
36
Reference C fault
Register 0x0D10, Bit 2
37
Reference CC fault
Register 0x0D11, Bit 2
38
Reference D fault
Register 0x0D12, Bit 2
39
Reference DD fault
Register 0x0D13, Bit 2
40 to 47
Unused
48
Reference A valid
Register 0x0D0C, Bit 3
49
Reference AA valid
Register 0x0D0D, Bit 3
50
Reference B valid
Register 0x0D0E, Bit 3
51
Reference BB valid
Register 0x0D0F, Bit 3
52
Reference C valid
Register 0x0D10, Bit 3
53
Reference CC valid
Register 0x0D11, Bit 3
54
Reference D valid
Register 0x0D12, Bit 3
55
Reference DD valid
Register 0x0D13, Bit 3
56 to 63
Unused
64
Reference A active
reference
Register 0x0D0B,
Bits[2:0]
65
Reference AA active
reference
Register0x0D0B,
Bits[2:0]
66
Reference B active
reference
Register 0x0D0B,
Bits[2:0]
67
Reference BB active
reference
Register 0x0D0B,
Bits[2:0]
68
Reference C active
reference
Register 0x0D0B,
Bits[2:0]
69
Reference CC active
reference
Register 0x0D0B,
Bits[2:0]
70
Reference D active
reference
Register 0x0D0B,
Bits[2:0]
71
Reference DD active
reference
Register 0x0D0B,
Bits[2:0]
72 to 79
Unused
80
Clock distribution sync
pulse
Register 0x0D03, Bit 3
81 to 127
Unused
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