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參數(shù)資料
| 型號： | AD9548/PCBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 1/112頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD9548 |
| 產(chǎn)品變化通告： | AD9548 Mask Change 20/Oct/2010 |
| 設(shè)計資源： | AD9548 Schematic AD9548 BOM AD9548 Eval Brd Layers |
| 標準包裝： | 1 |
| 主要目的： | 計時，時鐘發(fā)生器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | AD9548 |
| 主要屬性： | 62.5 ~ 450 MHz 輸出頻率 |
| 次要屬性： | SPI 和 I2C 兼容控制端口 |
| 已供物品： | 板 |
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Quad/Octal Input Network Clock
Generator/Synchronizer
Data Sheet
Rev. E
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringementsof patentsorother
rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
2009–2013 Analog Devices, Inc. All rights reserved.
FEATURES
Supports Stratum 2 stability in holdover mode
Supports reference switchover with phase build-out
Supports hitless reference switchover
Auto/manual holdover and reference switchover
4 pairs of reference input pins with each pair configurable as
a single differential input or as 2 independent single-
ended inputs
Input reference frequencies from 1 Hz to 750 MHz
Reference validation and frequency monitoring (1 ppm)
Programmable input reference switchover priority
30-bit programmable input reference divider
4 pairs of clock output pins with each pair configurable as a
single differential LVDS/LVPECL output or as 2 single-
ended CMOS outputs
Output frequencies up to 450 MHz
30-bit integer and 10-bit fractional programmable feedback
divider
Programmable digital loop filter covering loop bandwidths
from 0.001 Hz to 100 kHz
Optional low noise LC-VCO system clock multiplier
Optional crystal resonator for system clock input
On-chip EEPROM to store multiple power-up profiles
Software controlled power-down
88-lead LFCSP package
APPLICATIONS
Network synchronization
Cleanup of reference clock jitter
GPS 1 pulse per second synchronization
SONET/SDH clocks up to OC-192, including FEC
Stratum 2 holdover, jitter cleanup, and phase transient
control
Stratum 3E and Stratum 3 reference clocks
Wireless base station controllers
Cable infrastructure
Data communications
GENERAL DESCRIPTION
The AD9548 provides synchronization for many systems,
including synchronous optical networks (SONET/SDH). The
AD9548 generates an output clock synchronized to one of up to
four differential or eight single-ended external input references.
The digital PLL allows for reduction of input time jitter or phase
noise associated with the external references. The AD9548
continuously generates a clean (low jitter), valid output clock
even when all references have failed by means of a digitally
controlled loop and holdover circuitry.
The AD9548 operates over an industrial temperature range of
40°C to +85°C.
FUNCTIONAL BLOCK DIAGRAM
REFERENCE INPUTS
AND
MONITOR MUX
STATUS AND
CONTROL PINS
SERIAL CONTROL INTERFACE
(SPI or I2C)
EEPROM
DIGITAL
PLL
CLOCK DISTRIBUTION
SYNC
DAC
CLOCK
MULTIPLIER
STABLE
SOURCE
ANALOG
FILTER
AD9548
CHANNEL 0
DIVIDER
CHANNEL 1
DIVIDER
CHANNEL 2
DIVIDER
CHANNEL 3
DIVIDER
08
02
2-
00
1
Figure 1.
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| AD9548XCPZ | 制造商:Analog Devices 功能描述: |
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| AD9549A/PCBZ | 功能描述:BOARD EVALUATION FOR AD9549A RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 標準包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源 |
| AD9549ABCPZ | 功能描述:IC CLOCK GEN/SYNCHRONIZR 64LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標準包裝:1 系列:- 類型:時鐘/頻率發(fā)生器，多路復用器 PLL:是 主要目的:存儲器，RDRAM 輸入:晶體 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:1:2 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:Digi-Reel® 其它名稱:296-6719-6 |
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