參數資料
型號： AD9548/PCBZ
廠商： Analog Devices Inc
文件頁數： 69/112頁
文件大小： 0K
描述： BOARD EVAL FOR AD9548
產品變化通告： AD9548 Mask Change 20/Oct/2010
設計資源： AD9548 Schematic
AD9548 BOM
AD9548 Eval Brd Layers
標準包裝： 1
主要目的： 計時，時鐘發(fā)生器
嵌入式： 否
已用 IC / 零件： AD9548
主要屬性： 62.5 ~ 450 MHz 輸出頻率
次要屬性： SPI 和 I2C 兼容控制端口
已供物品： 板
AD9548
Data Sheet
Rev. E | Page 6 of 112
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
SYSTEM CLOCK PLL ENABLED
PLL Output Frequency Range
900
1000
MHz
Phase-Frequency Detector (PFD) Rate
150
MHz
Frequency Multiplication Range
6
255
Assumes valid system clock and PFD rates
VCO Gain
70
MHz/V
High Frequency Path
Input Frequency Range
100.1
500
MHz
Minimum Input Slew Rate
200
V/μs
Minimum limit imposed for jitter
performance
Frequency Divider Range
1
8
Binary steps (M = 1, 2, 4, 8)
Common-Mode Voltage
1
V
Internally generated
Differential Input Voltage Sensitivity
100
mV p-p
Minimum voltage across pins required to
ensure switching between logic states;
the instantaneous voltage on either pin
must not exceed the supply rails; can
accommodate single-ended input by ac
grounding unused input
Input Capacitance
3
pF
Single-ended, each pin
Input Resistance
2.5
k
Low Frequency Path
Input Frequency Range
3.5
100
MHz
Minimum Input Slew Rate
50
V/μs
Minimum limit imposed for jitter
performance
Common-Mode Voltage
1.2
V
Internally generated
Differential Input Voltage Sensitivity
100
mV p-p
Minimum voltage across pins required to
ensure switching between logic states;
the instantaneous voltage on either pin
must not exceed the supply rails; can
accommodate single-ended input by ac
grounding unused input
Input Capacitance
3
pF
Single-ended, each pin
Input Resistance
4
k
Crystal Resonator Path
Crystal Resonator Frequency Range
10
50
MHz
Fundamental mode, AT cut
Maximum Crystal Motional Resistance
100
See the System Clock Inputs section for
recommendations
DISTRIBUTION CLOCK INPUTS (CLKINP/CLKINN)
Table 7.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
DISTRIBUTION CLOCK INPUTS (CLKINP/CLKINN)
Input Frequency Range
62.5
500
MHz
Minimum Slew Rate
75
V/μs
Minimum limit imposed for jitter
performance.
Common-Mode Voltage
700
mV
Internally generated.
Differential Input Voltage Sensitivity
100
mV p-p
Capacitive coupling required; can
accommodate single-ended input
by ac grounding unused input; the
instantaneous voltage on either pin
must not exceed the supply rails.
Differential Input Power Sensitivity
15
dBm
The same as voltage sensitivity but
specified as power into a 50 load.
Input Capacitance
3
pF
Input Resistance
5
k
Each pin has a 2.5 k internal dc-
bias resistance.
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參數描述
AD9548XCPZ 制造商:Analog Devices 功能描述:
AD9549 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual Input Network Clock Generator/Synchronizer
AD9549/PCBZ 制造商:Analog Devices 功能描述:DUAL INPUT NETWORK CLOCK GEN/SYNCHRONIZER - Bulk
AD9549A/PCBZ 功能描述:BOARD EVALUATION FOR AD9549A RoHS:是 類別:編程器，開發(fā)系統 >> 評估演示板和套件 系列:- 標準包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源
AD9549ABCPZ 功能描述:IC CLOCK GEN/SYNCHRONIZR 64LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標準包裝:1 系列:- 類型:時鐘/頻率發(fā)生器，多路復用器 PLL:是 主要目的:存儲器，RDRAM 輸入:晶體 輸出:LVCMOS 電路數:1 比率 - 輸入:輸出:1:2 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:Digi-Reel® 其它名稱:296-6719-6
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