參數(shù)資料
型號： AD9548/PCBZ
廠商： Analog Devices Inc
文件頁數(shù)： 31/112頁
文件大?。?/td> 0K
描述： BOARD EVAL FOR AD9548
產(chǎn)品變化通告： AD9548 Mask Change 20/Oct/2010
設(shè)計資源： AD9548 Schematic
AD9548 BOM
AD9548 Eval Brd Layers
標準包裝： 1
主要目的： 計時，時鐘發(fā)生器
嵌入式： 否
已用 IC / 零件： AD9548
主要屬性： 62.5 ~ 450 MHz 輸出頻率
次要屬性： SPI 和 I2C 兼容控制端口
已供物品： 板
Data Sheet
AD9548
Rev. E | Page 25 of 112
Program the Clock Distribution Outputs
The clock distribution parameters reside in the 0x0400 register
address space. They include the following:
Output power-down control
Output enable (disabled by default)
Output synchronization
Output mode control
Output divider functionality
Program the Reference Inputs
The reference input parameters reside in the 0x0500 register
address space. They include the following:
Reference power-down
Reference logic family
Reference profile assignment control
Phase build-out control
Program the Reference Profiles
The reference profile parameters reside in the 0x0600 to 0x0700
register address space. They include the following:
Reference priority
Reference period
Reference period tolerance
Reference validation timer
Reference redetect timer
Digital loop-filter coefficients
Reference prescaler (R-divider)
Feedback dividers (S, U, and V)
Phase and frequency lock detector controls
Generate the Reference Acquisition
After the registers are programmed, issue an I/O update using
Register 0x0005, Bit 0 to invoke all of the register settings
programmed up to this point.
If the settings are programmed for manual profile assignment,
the DPLL locks to the first available reference that has the
highest priority. If the settings are programmed for automatic
profile assignment, then write to the reference profile detect
register (Address 0x0A0D) to select the state machines that
require starting. Next, issue an I/O update (Address 0x0005, Bit
0) to start the selected state machines. Upon completion of the
reference detection sequence, the DPLL locks to the first
available reference with the highest priority.
Generate the Output Clock
If the registers are programmed for automatic clock distribution
synchronization via DPLL phase or frequency lock, the syn-
thesized output signal appears at the clock distribution outputs
(assuming the output is enabled and that the DDS output signal
has been routed to the CLKIN input pins). Otherwise, set and
then clear the sync distribution bit (Address 0x0A02, Bit 1) or
use a multifunction pin input (if programmed accordingly) to
generate a clock distribution sync pulse, which causes the
synthesized output signal to appear at the clock distribution
outputs.
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參數(shù)描述
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AD9549/PCBZ 制造商:Analog Devices 功能描述:DUAL INPUT NETWORK CLOCK GEN/SYNCHRONIZER - Bulk
AD9549A/PCBZ 功能描述:BOARD EVALUATION FOR AD9549A RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 標準包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源
AD9549ABCPZ 功能描述:IC CLOCK GEN/SYNCHRONIZR 64LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標準包裝:1 系列:- 類型:時鐘/頻率發(fā)生器，多路復(fù)用器 PLL:是 主要目的:存儲器，RDRAM 輸入:晶體 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:1:2 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:Digi-Reel® 其它名稱:296-6719-6
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