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參數(shù)資料
| 型號： | 35007B |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | 18-pin Enhanced FLASH/EEPROM 8-bit Microcontroller |
| 中文描述： | 18針/ EEPROM的8位微控制器的閃存 |
| 文件頁數(shù)： | 9/88頁 |
| 文件大?。?/td> | 1495K |
| 代理商： | 35007B |
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2001 Microchip Technology Inc.
DS35007B-page 7
PIC16F84A
2.3
Special Function Registers
The Special Function Registers (Figure 2-2 and
Table 2-1) are used by the CPU and Peripheral
functions to control the device operation. These
registers are static RAM.
The special function registers can be classified into two
sets, core and peripheral. Those associated with the
core functions are described in this section. Those
related to the operation of the peripheral features are
described in the section for that specific feature.
TABLE 2-1:
SPECIAL FUNCTION REGISTER FILE SUMMARY
Addr
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
Power-on
RESET
Details
on page
Bank 0
00h
01h
02h
03h
INDF
TMR0
PCL
STATUS
(2)
Uses contents of FSR to address Data Memory (not a physical register)
8-bit Real-Time Clock/Counter
Low Order 8 bits of the Program Counter (PC)
---- ----
11
20
11
8
xxxx xxxx
0000 0000
IRP
RP1
RP0
TO
PD
Z
DC
C
0001 1xxx
04h
05h
06h
07h
08h
09h
0Ah
FSR
PORTA
(4)
PORTB
(5)
Indirect Data Memory Address Pointer 0
—
—
RB7
RB6
Unimplemented location, read as '0'
EEPROM Data Register
EEPROM Address Register
xxxx xxxx
11
16
18
—
—
RB5
RA4/T0CKI
RB4
RA3
RB3
RA2
RB2
RA1
RB1
RA0
RB0/INT
xxxx xxxx
---x xxxx
—
—
EEDATA
EEADR
xxxx xxxx
13,14
13,14
11
xxxx xxxx
PCLATH
—
—
—
Write Buffer for upper 5 bits of the PC
(1)
---0 0000
0Bh
Bank 1
80h
81h
INTCON
GIE
EEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
10
INDF
Uses Contents of FSR to address Data Memory (not a physical register)
---- ----
11
9
OPTION_REG
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
82h
83h
PCL
STATUS
(2)
Low order 8 bits of Program Counter (PC)
0000 0000
11
8
IRP
RP1
RP0
TO
PD
Z
DC
C
0001 1xxx
84h
85h
86h
87h
88h
89h
FSR
TRISA
TRISB
Indirect data memory address pointer 0
—
—
PORTB Data Direction Register
Unimplemented location, read as '0'
—
—
xxxx xxxx
11
16
18
—
13
14
—
PORTA Data Direction Register
---1 1111
1111 1111
—
—
EECON1
—
EEIF
WRERR
WREN
WR
RD
---0 x000
EECON2
EEPROM Control Register 2 (not a physical register)
---- ----
0Ah
PCLATH
—
—
—
Write buffer for upper 5 bits of the PC
(1)
---0 0000
11
0Bh
Legend:
x
= unknown,
u
= unchanged.
-
= unimplemented, read as '0',
q
= value depends on condition
Note
1:
The upper byte of the program counter is not directly accessible. PCLATH is a slave register for PC<12:8>. The contents
of PCLATH can be transferred to the upper byte of the program counter, but the contents of PC<12:8> are never trans-
ferred to PCLATH.
2:
The TO and PD status bits in the STATUS register are not affected by a MCLR Reset.
3:
Other (non power-up) RESETS include: external RESET through MCLR and the Watchdog Timer Reset.
4:
On any device RESET, these pins are configured as inputs.
5:
This is the value that will be in the port output latch.
INTCON
GIE
EEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
10
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