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參數(shù)資料
| 型號： | 35007B |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | 18-pin Enhanced FLASH/EEPROM 8-bit Microcontroller |
| 中文描述： | 18針/ EEPROM的8位微控制器的閃存 |
| 文件頁數(shù)： | 16/88頁 |
| 文件大小： | 1495K |
| 代理商： | 35007B |
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PIC16F84A
DS35007B-page 14
2001 Microchip Technology Inc.
3.1
Reading the EEPROM Data
Memory
To read a data memory location, the user must write the
address to the EEADR register and then set control bit
RD (EECON1<0>). The data is available, in the very
next cycle, in the EEDATA register; therefore, it can be
read in the next instruction. EEDATA will hold this value
until another read or until it is written to by the user
(during a write operation).
EXAMPLE 3-1:
DATA EEPROM READ
3.2
Writing to the EEPROM Data
Memory
To write an EEPROM data location, the user must first
write the address to the EEADR register and the data
to the EEDATA register. Then the user must follow a
specific sequence to initiate the write for each byte.
EXAMPLE 3-2:
DATA EEPROM WRITE
The write will not initiate if the above sequence is not
exactly followed (write 55h to EECON2, write AAh to
EECON2, then set WR bit) for each byte. We strongly
recommend that interrupts be disabled during this
code segment.
Additionally, the WREN bit in EECON1 must be set to
enable write. This mechanism prevents accidental writes
to data EEPROM due to errant (unexpected) code exe-
cution (i.e., lost programs). The user should keep the
WREN bit clear at all times, except when updating
EEPROM. The WREN bit is not cleared by hardware.
After a write sequence has been initiated, clearing the
WREN bit will not affect this write cycle. The WR bit will
be inhibited from being set unless the WREN bit is set.
At the completion of the write cycle, the WR bit is
cleared in hardware and the EE Write Complete
Interrupt Flag bit (EEIF) is set. The user can either
enable this interrupt or poll this bit. EEIF must be
cleared by software.
3.3
Write Verify
Depending on the application, good programming
practice may dictate that the value written to the Data
EEPROM should be verified (Example 3-3) to the
desired value to be written. This should be used in
applications where an EEPROM bit will be stressed
near the specification limit.
Generally, the EEPROM write failure will be a bit which
was written as a ’0’, but reads back as a ’1’ (due to
leakage off the bit).
EXAMPLE 3-3:
BCF
:
:
MOVF EEDATA,W
BSF
READ
BSF
WRITE VERIFY
STATUS,RP0 ; Bank 0
TABLE 3-1:
REGISTERS/BITS ASSOCIATED WITH DATA EEPROM
BCF STATUS, RP0 ; Bank 0
MOVLW CONFIG_ADDR ;
MOVWF EEADR ; Address to read
BSF STATUS, RP0 ; Bank 1
BSF EECON1, RD ; EE Read
BCF STATUS, RP0 ; Bank 0
MOVF EEDATA, W ; W = EEDATA
BSF STATUS, RP0 ; Bank 1
BCF INTCON, GIE ; Disable INTs.
BSF EECON1, WREN ; Enable Write
MOVLW 55h ;
MOVWF EECON2 ; Write 55h
MOVLW AAh ;
MOVWF EECON2 ; Write AAh
BSF EECON1,WR ; Set WR bit
; begin write
BSF INTCON, GIE ; Enable INTs.
R
S
; Any code
; can go here
; Must be in Bank 0
STATUS,RP0 ; Bank 1
EECON1, RD
; YES, Read the
; value written
BCF
STATUS, RP0 ; Bank 0
;
; Is the value written
; (in W reg) and
; read (in EEDATA)
; the same
;
;
; Is difference 0
; NO, Write error
SUBWF EEDATA, W
BTFSS STATUS, Z
GOTO WRITE_ERR
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
Power-on
Reset
Value on
all other
RESETS
08h
09h
88h
89h
Legend:
x
= unknown,
u
= unchanged,
-
= unimplemented, read as '0',
q
= value depends upon condition.
Shaded cells are not used by data EEPROM.
EEDATA
EEADR
EECON1
EECON2
EEPROM Data Register
EEPROM Address Register
—
—
EEPROM Control Register 2
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
—
EEIF
WRERR
WREN
WR
RD
---0 x000 ---0 q000
---- ---- ---- ----
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