參數(shù)資料
型號(hào)： 35007B
廠商： Microchip Technology Inc.
英文描述： 18-pin Enhanced FLASH/EEPROM 8-bit Microcontroller
中文描述： 18針/ EEPROM的8位微控制器的閃存
文件頁數(shù)： 10/88頁
文件大?。?/td> 1495K
代理商： 35007B
PIC16F84A
DS35007B-page 8
2001 Microchip Technology Inc.
2.3.1
STATUS REGISTER
The STATUS register contains the arithmetic status of
the ALU, the RESET status and the bank select bit for
data memory.
As with any register, the STATUS register can be the
destination for any instruction. If the STATUS register is
the destination for an instruction that affects the Z, DC
or C bits, then the write to these three bits is disabled.
These bits are set or cleared according to device logic.
Furthermore, the TO and PD bits are not writable.
Therefore, the result of an instruction with the STATUS
register as destination may be different than intended.
For example,
CLRF STATUS
will clear the upper three
bits and set the Z bit. This leaves the STATUS register
as
000u u1uu
(where
u
= unchanged).
Only the
BCF, BSF, SWAPF
and
MOVWF
instructions
should be used to alter the STATUS register (Table 7-2),
because these instructions do not affect any status bit.
REGISTER 2-1:
STATUS REGISTER (ADDRESS 03h, 83h)
Note 1:
The IRP and RP1 bits (STATUS<7:6>)
are not used by the PIC16F84A and
should be programmed as cleared. Use of
these bits as general purpose R/W bits is
NOT recommended, since this may affect
upward compatibility with future products.
2:
The C and DC bits operate as a borrow
and digit borrow out bit, respectively, in
subtraction. See the
SUBLW
and
SUBWF
instructions for examples.
3:
When the STATUS register is the
destination for an instruction that affects
the Z, DC or C bits, then the write to these
three bits is disabled. The specified bit(s)
will be updated according to device logic
R/W-0
IRP
bit 7
R/W-0
RP1
R/W-0
RP0
R-1
TO
R-1
PD
R/W-x
Z
R/W-x
DC
R/W-x
C
bit 0
bit 7-6
bit 5
Unimplemented:
Maintain as ‘
0
’
RP0
: Register Bank Select bits (used for direct addressing)
01
= Bank 1 (80h - FFh)
00
= Bank 0 (00h - 7Fh)
TO
: Time-out bit
1
= After power-up,
CLRWDT
instruction, or
SLEEP
instruction
0
= A WDT time-out occurred
PD
: Power-down bit
1
= After power-up or by the
CLRWDT
instruction
0
= By execution of the
SLEEP
instruction
Z
: Zero bit
1
= The result of an arithmetic or logic operation is zero
0
= The result of an arithmetic or logic operation is not zero
DC
: Digit carry/borrow bit (
ADDWF
,
ADDLW,SUBLW,SUBWF
instructions) (for borrow, the polarity
is reversed)
1
= A carry-out from the 4th low order bit of the result occurred
0
= No carry-out from the 4th low order bit of the result
C
: Carry/borrow bit (
ADDWF
,
ADDLW,SUBLW,SUBWF
instructions) (for borrow, the polarity is
reversed)
1
= A carry-out from the Most Significant bit of the result occurred
0
= No carry-out from the Most Significant bit of the result occurred
Note:
A subtraction is executed by adding the two’s complement of the second operand.
For rotate (
RRF
,
RLF
) instructions, this bit is loaded with either the high or low order
bit of the source register.
bit 4
bit 3
bit 2
bit 1
bit 0
Legend:
R = Readable bit
- n = Value at POR
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared
x = Bit is unknown
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