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參數(shù)資料
| 型號： | 35007B |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | 18-pin Enhanced FLASH/EEPROM 8-bit Microcontroller |
| 中文描述： | 18針/ EEPROM的8位微控制器的閃存 |
| 文件頁數(shù)： | 21/88頁 |
| 文件大?。?/td> | 1495K |
| 代理商： | 35007B |
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2001 Microchip Technology Inc.
DS35007B-page 19
PIC16F84A
5.0
TIMER0 MODULE
The Timer0 module timer/counter has the following
features:
8-bit timer/counter
Readable and writable
Internal or external clock select
Edge select for external clock
8-bit software programmable prescaler
Interrupt-on-overflow from FFh to 00h
Figure 5-1 is a simplified block diagram of the Timer0
module.
Additional information on timer modules is available in
the
PICmicro
Mid-Range
(DS33023).
Reference
Manual
5.1
Timer0 Operation
Timer0 can operate as a timer or as a counter.
Timer mode is selected by clearing bit T0CS
(OPTION_REG<5>). In Timer mode, the Timer0 mod-
ule will increment every instruction cycle (without pres-
caler). If the TMR0 register is written, the increment is
inhibited for the following two instruction cycles. The
user can work around this by writing an adjusted value
to the TMR0 register.
Counter mode is selected by setting bit T0CS
(OPTION_REG<5>). In Counter mode, Timer0 will
increment, either on every rising or falling edge of pin
RA4/T0CKI. The incrementing edge is determined by
the
Timer0
Source
Edge
(OPTION_REG<4>). Clearing bit T0SE selects the ris-
ing edge. Restrictions on the external clock input are
discussed below.
Select
bit,
T0SE
When an external clock input is used for Timer0, it must
meet certain requirements. The requirements ensure
the external clock can be synchronized with the internal
phase clock (T
OSC
). Also, there is a delay in the actual
incrementing of Timer0 after synchronization.
Additional information on external clock requirements
is available in the PICmicro Mid-Range Reference
Manual, (DS33023).
5.2
Prescaler
An 8-bit counter is available as a prescaler for the Timer0
module, or as a postscaler for the Watchdog Timer,
respectively (Figure 5-2). For simplicity, this counter is
being referred to as “prescaler” throughout this data
sheet. Note that there is only one prescaler available
which is mutually exclusively shared between the Timer0
module and the Watchdog Timer. Thus, a prescaler
assignment for the Timer0 module means that there is no
prescaler for the Watchdog Timer, and vice-versa.
The prescaler is not readable or writable.
The PSA and PS2:PS0 bits (OPTION_REG<3:0>)
determine the prescaler assignment and prescale ratio.
Clearing bit PSA will assign the prescaler to the Timer0
module. When the prescaler is assigned to the Timer0
module, prescale values of 1:2, 1:4, ..., 1:256 are
selectable.
Setting bit PSA will assign the prescaler to the Watchdog
Timer (WDT). When the prescaler is assigned to the
WDT, prescale values of 1:1, 1:2, ..., 1:128 are selectable.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g.,
CLRF 1, MOVWF 1,
BSF 1,
etc.) will clear the prescaler. When assigned to
WDT, a
CLRWDT
instruction will clear the prescaler
along with the WDT.
FIGURE 5-1:
TIMER0 BLOCK DIAGRAM
Note:
Writing to TMR0 when the prescaler is
assigned to Timer0 will clear the prescaler
count, but will not change the prescaler
assignment.
Note
1:
T0CS, T0SE, PSA, PS2:PS0 (OPTION_REG<5:0>).
2:
The prescaler is shared with Watchdog Timer (refer to Figure 5-2 for detailed block diagram).
RA4/T0CKI
pin
T0SE
0
1
1
0
T0CS
F
OSC
/4
Programmable
Prescaler
Sync with
Internal
Clocks
TMR0
PS
OUT
(2 Cycle Delay)
PS
OUT
Data Bus
8
PSA
PS2, PS1, PS0
Set Interrupt
Flag bit T0IF
on Overflow
3
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