- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄25056 > 0W888-002-XTP (ON SEMICONDUCTOR) BelaSigna 250 - 16 bit Audio Processor, Full Stereo 2-in, 2-out; Package: LFBGA 64, 7x7; No of Pins: 64; Container: Tape and Reel; Qty per Container: 1500 PDF資料下載
參數(shù)資料
| 型號(hào)： | 0W888-002-XTP |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | BelaSigna 250 - 16 bit Audio Processor, Full Stereo 2-in, 2-out; Package: LFBGA 64, 7x7; No of Pins: 64; Container: Tape and Reel; Qty per Container: 1500 |
| 中文描述： | 0-BIT, 50 MHz, MIXED DSP, PBGA64 |
| 封裝： | 7 X 7 MM, GREEN, LFBGA-64 |
| 文件頁數(shù)： | 8/34頁 |
| 文件大?。?/td> | 935K |
| 代理商： | 0W888-002-XTP |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁當(dāng)前第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁
Rev. 7 | Page 16 of 34 | www.onsemi.com
BelaSigna 250
In the case where the WOLA coprocessor and the IOP no longer work together as a result of a low battery condition, an IOP end-of-
battery-life auto-mute feature is available.
The IOP can be configured to access data in the FIFOs in four different audio modes that are shown in Figure 8.
Mono mode: Input samples are stored sequentially in the input FIFO. Output samples are stored sequentially in the output
FIFO.
Simple stereo mode: Input samples from the two channels are interleaved in the input FIFO. Output samples for the single
output channel are stored in the lower part of the output FIFO.
Digital mixed mode: Input samples from the two channels are stored in each half of the input FIFO. Output samples for the
single output channel are stored in the lower half of the output FIFO.
Full stereo mode: Input samples from the two channels are interleaved in the input FIFO. Output samples for the two output
channels are also interleaved in the output FIFO.
Figure 8: Audio Modes
3.4 Other Digital Blocks and Functions
3.4.1. RAM and ROM
There are 20-Kwords of on-chip program and data RAM on BelaSigna 250. These are divided into three entities: a 12-Kword program
memory, and two 4-Kword data memories ("X" and "Y", as are common in a dual-Harvard architecture).
There are also three RAM banks that are shared between the RCore and WOLA coprocessor. These memory banks contain the input
and output FIFOs, gain tables for the WOLA coprocessor, temporary memory for WOLA calculations, WOLA coprocessor results, and
the WOLA coprocessor microcode.
There is a 128-word lookup table (LUT) ROM that contains log2(x), 2
x, 1/x and sqrt(x) values, and a 1-Kword program ROM that is used
during booting and configuration of the system.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 0X860 | OSCILLOSCOPE 100MHz ANALOGUE |
| 2-5174339-5 | 68 CONTACT(S), MALE, STRAIGHT TELECOM AND DATACOM CONNECTOR, SOLDER |
| 2-5174339-4 | 50 CONTACT(S), MALE, STRAIGHT TELECOM AND DATACOM CONNECTOR, SOLDER |
| 2-640445-1 | 21 CONTACT(S), MALE, STRAIGHT TWO PART BOARD CONNECTOR, SOLDER |
| 208006-1 | 9 CONTACT(S), MALE, D SUBMINIATURE CONNECTOR, SOLDER, PLUG |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 0W912 | 制造商:Intel 功能描述:MBRD, SUPERMANIII, DELL |
| 0W9495 | 功能描述:電纜組件 DC POWER cbl RoHS:否 制造商:Molex 產(chǎn)品:Power Assemblies 類型:Cable Assembly 連接器端口 A:No Connector 連接器端口 A 管腳計(jì)數(shù):4 連接器端口 B:No Connector 連接器端口 B 管腳計(jì)數(shù): 型式:Male 線規(guī) - 美國(guó)線規(guī)（AWG）:20, 28 長(zhǎng)度:0.305 m 顏色:Black, Red |
| 0WCGA-002-XTP | 制造商:AppliedMicro 功能描述: |
| 0WCHY117 | 制造商:The Cherry Corporation 功能描述: |
| 0WCHY403 | 制造商:The Cherry Corporation 功能描述: |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。