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參數(shù)資料
| 型號： | 0W888-002-XTP |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | BelaSigna 250 - 16 bit Audio Processor, Full Stereo 2-in, 2-out; Package: LFBGA 64, 7x7; No of Pins: 64; Container: Tape and Reel; Qty per Container: 1500 |
| 中文描述： | 0-BIT, 50 MHz, MIXED DSP, PBGA64 |
| 封裝： | 7 X 7 MM, GREEN, LFBGA-64 |
| 文件頁數(shù)： | 10/34頁 |
| 文件大?。?/td> | 935K |
| 代理商： | 0W888-002-XTP |
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Rev. 7 | Page 18 of 34 | www.onsemi.com
BelaSigna 250
3.4.4. Watchdog Timer
The watchdog timer is a programmable hardware timer that operates from the system clock and is used to ensure system sanity. It is
always active and must be periodically acknowledged as a check that an application is still running. Once the watchdog times out, it
generates an interrupt. If left to time out a second consecutive time without acknowledgement, BelaSigna 250 will fully reset itself.
3.4.5. Interrupts
The RCore has a single interrupt channel that serves 13 interrupt sources in a prioritized manner. The interrupt controller also handles
interrupt acknowledge flags. Every interrupt source has its own interrupt vector. Furthermore, the priority scheme of the interrupt
sources can be modified. Refer to Table 8 for a description of all interrupts.
Table 8: Interrupt Descriptions
Interrupt
Description
WOLA_DONE
WOLA function done
IO_BLOCK_FULL
IOP interrupt
GP_TIMER
General-purpose timer interrupt
WATCHDOG_TIMER
Watchdog timer interrupt
SPI_INTERFACE
SPI interface interrupt
IR
IR remote interrupt
EXT3_RX
EXT3 register receive interrupt
EXT3_TX
EXT3 register transmit interrupt
GPIO
User configurable GPIO interrupt
TWSS_INTERFACE
Two-wire synchronous serial interface interrupt
UART_RX
General-purpose UART receive interrupt
UART_TX
General-purpose UART transmit interrupt
PCM
PCM interface interrupt
3.5 Analog Blocks
3.5.1. Input Stage
The analog audio input stage is comprised of two individual channels. For each channel, the selected one out of the four possible inputs
is routed to the input of the programmable preamplifier that can be configured for bypass or gain values of 12 to 30dB (3dB steps).
The analog signal is filtered to remove frequencies above 20kHz before it is passed into the high-fidelity 16-bit oversampling
A/D
converter. Subsequently, any necessary sample rate decimation is performed to downsample the signal to the desired sampling rate.
During decimation the level of the signal can be adjusted digitally for optimal gain matching between the two input channels. Any
undesired DC component can be removed by a configurable DC-removal filter that is part of the decimation circuitry. The DC removal
filter can be configured for bypass or cut-off frequencies at 5, 10 and 20Hz.
A built-in feature allows a sampling delay to be configured between channel zero and channel one (or vice versa). This is useful in
beam-forming applications.
Note: Both preamplifiers can be daisy-chained to increase the potential gain, but the signal has to be routed externally to the chip.
For power consumption savings either of the input channels can be disabled via software. A different input must be selected for each
channel. The input stage is shown in Figure 10.
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