參數(shù)資料
型號(hào)： 0W888-002-XTP
廠商： ON SEMICONDUCTOR
元件分類(lèi)： 數(shù)字信號(hào)處理
英文描述： BelaSigna 250 - 16 bit Audio Processor, Full Stereo 2-in, 2-out; Package: LFBGA 64, 7x7; No of Pins: 64; Container: Tape and Reel; Qty per Container: 1500
中文描述： 0-BIT, 50 MHz, MIXED DSP, PBGA64
封裝： 7 X 7 MM, GREEN, LFBGA-64
文件頁(yè)數(shù)： 33/34頁(yè)
文件大?。?/td> 935K
代理商： 0W888-002-XTP
Rev. 7 | Page 8 of 34 | www.onsemi.com
BelaSigna 250
2.1.4. Recommended Ground Design Strategy
The ground plane should be partitioned into two: the analog ground plane (AGND) and the digital ground plane (DGND). These two
planes should be connected together at a single point, known as the star point. The star point should be located at the ground terminal
of a capacitor on the output of the power regulator as illustrated in Figure 4.
The DGND plane is used as the ground return for digital circuits and should be placed under digital circuits. The AGND plane should be
kept as noise-free as possible. It is used as the ground return for analog circuits and it should surround analog components and pins. It
should not be connected to or placed under any noisy circuits such as RF chips, switching supplies or digital pads of BelaSigna 250
itself. Analog ground returns associated with the audio output stage should connect back to the star point on separate individual traces.
For more information on the recommended ground design strategy, see Table 4 and Table 5.
In some designs, space constraints may make separate ground planes impractical. In this case a star configuration strategy should be
used. Each analog ground return should connect to the star point with separate traces.
AGND
Voltage Regulator
STAR
POINT
V_BATTERY
1uF
10nF
1uF
10uF
U8
BelaSigna 250
GPIO[14]/PCM_FRAME/REMOTE
LSAD[3]/GPIO[7]
VD
D
C
DG
ND
SPI_CLK
GPIO[1]/I2S_IND
GPIO[2]/I2S_INA
TWSS_DATA
GPIO[11]/PCM_CLK
GPIO[12]/PCM_SERI
TWSS_CLK
GPIO[13]/PCM_SERO
AOR
EXT_CLK
RCVRBAT
VDBL
C
AP1
AI1/LOUT
AI0
SPI_CS
LSAD[2]/GPIO[6]
LSAD[1]/GPIO[5]/I2S_OUTA
VREG
AGN
D
[0
]
VBAT
RCVR0+
RCVR0-
AIR
DEBUG_TX
DEBUG_RX
SPI_SERO
LSAD[0]/GPIO[4]/I2S_OUTD
GPIO[3]/NCLK_DIV_RESET/I2S_FA
RCVRGND
AO1/RCVR1-
GPIO[0]/I2S_FD
SPI_SERI
LSAD[4]/GPIO[8]/UART_TX
LSAD[5]/GPIO[9]/UART_RX
GPIO[10]/UCLK
C
AP0
AI2
AI3
AO0/RCVR1+
AGN
D
[1
]
GPIO[15]
AI_RC
C14
10uF
U6
AT25256A
CS
1
SO
2
WP
3
Vs
s
4
SI
5
SCK
6
HOLD
7
Vc
c
8
PHOTODIODE
10nF
R
100nF
GPIO7
GPIO1
GPIO2
GPIO13
GPIO5
GPIO3
GPIO6
GPIO11
GPIO14
GPIO4
GPIO9
GPIO8
GPIO0
GPIO10
GPIO12
MIC1
MIC2
MIC0
AO0
GPIO15
MIC3
RCVR0+
AO1
DEBUG_TX
DEBUG_RX
RCVR0-
EXT_CLK
TWSS_CLK
TWSS_DATA
GNDD
1.8V
GNDD
1.8V
VDDC
GNDD
1.8V
+
GNDD
LFBGA64
Figure 4: Schematic of Ground Scheme
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