參數(shù)資料
型號(hào)： 0W888-002-XTP
廠商： ON SEMICONDUCTOR
元件分類(lèi)： 數(shù)字信號(hào)處理
英文描述： BelaSigna 250 - 16 bit Audio Processor, Full Stereo 2-in, 2-out; Package: LFBGA 64, 7x7; No of Pins: 64; Container: Tape and Reel; Qty per Container: 1500
中文描述： 0-BIT, 50 MHz, MIXED DSP, PBGA64
封裝： 7 X 7 MM, GREEN, LFBGA-64
文件頁(yè)數(shù)： 14/34頁(yè)
文件大?。?/td> 935K
代理商： 0W888-002-XTP
Rev. 7 | Page 21 of 34 | www.onsemi.com
BelaSigna 250
The user clock (UCLK) can be used to provide a clock signal to an external component, independently from the EXT_CLK pin
functionality. It can be derived from SYS_CLK with a variety of derivation factors, or can be connected to MCLK or even PCLK. One
instance in which it is beneficial to use this feature is when a continuous external clock output is required but when EXT_CLK is already
being used to provide SYS_CLK to BelaSigna 250.
3.6 Power Supply Unit
3.6.1. Voltage Modes
BelaSigna 250 can operate in three different power supply modes: high, low and double voltage. These modes allow BelaSigna 250 to
integrate into a wider variety of devices with a range of voltage supplies and communications levels. The power supply modes are
described below:
High voltage (HV) power supply mode: BelaSigna 250 operates from a nominal supply of 1.8V on VBAT, but this can scale
depending on available supply. All digital sections of the system, including digital I/O pads, run from the same voltage as
supplied on VBAT. This mode is preferable in designs where a very stable supply is available and BelaSigna 250 will be
interfacing to other digital systems at the same voltage. This mode is also necessary for higher than 5.12MHz system clocks.
Low voltage (LV) power supply mode: BelaSigna 250 operates from a nominal supply of 1.25V. The WOLA, the RCore and
all digital I/O pads run from a 1V regulated supply. The low voltage operation of the processing cores is very power-efficient,
but the system clock should be kept under 5.12MHz to ensure proper operation.
Double voltage (DV) power supply mode: BelaSigna 250 operates from a nominal supply of 1.25V. The WOLA, the RCore
and all digital I/O pads run from the on-chip charge pump which regulates internal voltage up to 2V. This allows BelaSigna 250
to communicate with higher voltage systems like a 1.8V EEPROM when running on a lower supply voltage. However, a
specific level translation mechanism has been designed to allow BelaSigna 250 to communicate with an SPI EEPROM in low
voltage mode as well. This voltage mode is not suitable for normal operation, processing in this mode may result in audible
audio artifacts. Most BelaSigna 250 applications run in high voltage mode.
3.6.2. Power-on-Reset (POR) and Booting Sequence
At POR, all control registers and RCore registers are put into known default states. During the power-on procedure, all audio outputs
are muted; all RCore registers and all control registers (analog and digital) are set to default values. (Please contact ON Semiconductor
for more information on default values associated with each control register.)
BelaSigna 250 boots in a two-stage boot sequence. The program ROM begins loading the bootloader from an external EEPROM
200ms after power is applied to the chip. In this process the program ROM checks the bootloader for validity, which in turn ensures the
file system validity. If the file structure is validated, the bootloader is written to PRAM. In case of an error while reading the external
EEPROM, all outputs are muted. The system restarts approximately every second and attempts to reboot.
Once the bootloader is loaded into PRAM the program counter is set to point to the beginning of the bootloader code. Subsequently,
the signal-processing application that is stored in the EEPROM is downloaded to PRAM by the bootloader. The boot process generally
takes less than one second. ON Semiconductor provides a standard full-feature bootloader. A graphical representation of this booting
sequence can be seen in Figure 12.
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