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參數(shù)資料
| 型號： | 0W888-002-XTP |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | BelaSigna 250 - 16 bit Audio Processor, Full Stereo 2-in, 2-out; Package: LFBGA 64, 7x7; No of Pins: 64; Container: Tape and Reel; Qty per Container: 1500 |
| 中文描述： | 0-BIT, 50 MHz, MIXED DSP, PBGA64 |
| 封裝： | 7 X 7 MM, GREEN, LFBGA-64 |
| 文件頁數(shù)： | 5/34頁 |
| 文件大小： | 935K |
| 代理商： | 0W888-002-XTP |
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Rev. 7 | Page 13 of 34 | www.onsemi.com
BelaSigna 250
Table 6: Instruction Set (Continued)
Instruction
Description
Instruction
Description
ANDI A, IMM
AND IMM with AH to AH
INC Reg [,Cond]
Increment register on condition
ANSI A, SIMM
AND unsigned SIMM with AH to AH
INC (Rij) [,Cond]
Increment memory on condition
BRA PRAM [,Cond]
Branch to new address on condition
LD Rc, Rc
Load Rc register with Rc register
BREAK
Stop the DSP for debugging purposes
LD Reg, Reg
Load register with register
CALL PRAM [,Cond] [,B]
Push PC and branch to new address on
condition
LD Reg, (Rij)
Load register with memory
CLB A
Calculate the leading bits on A
LD (Rij), Reg
Load memory with register
CLR A [,DW]
Clear accumulator
LD (Ri), (Rj)
Transfer Y mem data to X mem
CLR Reg
Clear register
LD (Rj), (Ri)
Transfer X mem data to Y mem
CMP A, Reg [,C]
Compare register to A
LD A, DRAM [,B]
Load A with (DRAM)
CMP A, (Rij) [,C]
Compare memory to A
LD DRAM, A [,B]
Load (DRAM) with A
CMP A, DRAM [,B]
Compare (DRAM) to A
LD Rc, (Rij)
Load Rc register with memory
CMP A, (Rij)p [,C]
Compare program memory to A
LD (Rij), Rc
Load memory with Rc register
CMP A, Rc [,C]
Compare Rc register to A
LD Reg, (Rij)p
Load register with program memory
CMPI A, IMM [,C]
Compare IMM to A
LD (Rij)p, Reg
Load program memory with register
CMSI A, SIMM
Compare signed SIMM to A
LD Reg, (Reg)p
Load register with program memory via
register
CMPL A [,Cond] [,DW]
Calculate logical inverse of A on condition
LD Reg, Rc
Load register with Rc register
DADD [Cond] [,P]
Add PH | PL to A, update PH | PL on condition
LD Rc, Reg
Load Rc register with register
DBNZ0/1 PRAM
Branch to new address if LC0/1 <> 0
LDI Reg, IMM
Load register with IMM
LDI Rc, IMM
Load Rc register with IMM
PUSH Rc [,B]
Push Rc register on stack
LDI (Rij), IMM
Load memory with IMM
PUSH IMM [,B]
Push IMM on stack
LDSI LC0/1 SIMM
Load loop counter with 16-bit unsigned SIMM
REP n
Repeat next instruction n+1 times
(9-bit unsigned)
LDSI A, SIMM
Load A with signed SIMM
REP Reg
Repeat next instruction Reg+1 times
LDSI Rij, SIMM
Load pointer register with unsigned SIMM
REP (Rij)
Repeat next instruction (Rij)+1 times
MLD (Rj), (Ri) [,SQ]
Multiplier load and clear A
RES Reg, Bit
Clear bit in register
MLD Reg, (Ri) [,SQ]
Multiplier load and clear A
RES (Rij), Bit
Clear bit in memory
MODR Rj, Ri
Pointer register modification
RET [B]
Return from subroutine
MPYA (Rj), (Ri) [,SQ]
Multiplier load and accumulate
RND A
Round A with AL
MPYA Reg, (Ri) [,SQ]
Multiplier load and accumulate
SET Reg, Bit
Set bit in register
MPYS (Rj), (Ri) [,SQ]
Multiplier load and accumulate negative
SET (Rij), Bit
Set bit in memory
MPYS Reg, (Ri) [,SQ]
Multiplier load and accumulate negative
SET_IE
Set interrupt enable flag
MSET (Rj), (Ri) [,SQ]
Multiplier load
SHFT n
Shift A by +/- n bits (6-bit signed)
MSET Reg, (Ri) [,SQ]
Multiplier load
SHFT A [,Cond] [,INV] Shift A by EXP bits on condition
MUL [Cond] [,A] [,P]
Update A and/or PH | PL with X*Y on
condition
SLEEP [IE]
Sleep
NEG A [,Cond] [,DW]
Calculate negative value of A on condition
SUB A, Reg [,C]
Subtract register from A
NOP
No operation
SUB A, (Rij) [,C]
Subtract memory from A
Architecture Overview
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