
79
APPENDIX B INDEX
APPENDIX B INDEX
[A]
A1.......................................................................23
A2-A27 ...............................................................22
A28-A31 .............................................................22
address space....................................................27
application ..........................................................16
ASEL ..................................................................26
[B]
barrel shifter .......................................................19
BCLK..................................................................26
BCYST ...............................................................24
BE0, BE1............................................................23
BE0-BE3 ............................................................23
BE2 ....................................................................23
BE3 ....................................................................23
BH ......................................................................23
block diagram .....................................................19
bus interface unit ......................................... 19, 20
[C]
chip select function.............................................30
clock controller ..................................... 19, 20, 65
CM......................................................................68
CMODE..............................................................26
CPU core..................................................... 19, 20
CS0-CS3 ............................................................22
[D]
D0-D31...............................................................22
data cache..........................................................19
data RAM ...........................................................19
[G]
general-purpose register....................................19
GND ...................................................................26
[H]
halt acknowledge cycle ......................................66
HALT instruction .......................................... 65, 66
HLDAK ...............................................................25
HLDRQ...............................................................25
[I]
I/O space............................................................29
IC1......................................................................26
IC2......................................................................26
IC3......................................................................26
initial register value ............................................64
instruction cache ................................................19
instruction RAM..................................................19
INT .....................................................................25
internal I/O area .................................................29
internal memory .................................................20
internal unit ........................................................20
interrupt ..............................................................61
interrupt controller ....................................... 19, 20
interrupt level......................................................61
INTV0-INTV3............................................... 25, 61
[M]
maskable interrupt..............................................61
memory map ......................................................28
memory space ...................................................27
[N]
NMI.....................................................................25
nonmaskable interrupt........................................62
[O]
ordering information ...........................................16
[P]
pin configuration.................................................17
pin function.........................................................21