參數(shù)資料
型號: μPD705100
廠商: NEC Corp.
英文描述: 32 Bit Microprocessor(32 位微處理器)
中文描述: 32位微處理器(32位微處理器)
文件頁數(shù): 58/81頁
文件大小: 441K
代理商: ΜPD705100
58
V830
TM
USER'S MANUAL
5.4.2 Bus Hold
A bus master other than the V830 can use HLDRQ to request bus mastership from the V830. In 16-bit
bus mode, HLDRQ is sampled at the rising edge of the bus clock in the Ts, Tw2, or Tb8 state and READY
(input) is sampled when that state ends. If both signals are active, the bus enters the Ti state. In this state,
HLDAK is activated and HLDRQ is again sampled at the rising edge of the bus clock. If HLDRQ is active,
the bus enters the Th state (bus hold state).
In the Th state, the bus is floating. Provided HLDRQ remains active, the bus will remain in the Th state.
When HLDRQ becomes inactive, the bus exits from the Th state such that the V830 regains bus mastership
and enters the Ti state. While the bus is locked, it does not accept bus hold requests until immediately before
the last bus cycle. In the last bus cycle, the bus accepts a bus hold request.
Figure 5-13. Bus Hold
Ts
Ti
Th
Th
Th
Th
Th
Th
Th
Ti
Ta
Th
Ta
BCLK (input)
Note 1
D0-D15 (I/O)
(Write)
CS0-CS3 (output)
Note 2
ST0-ST3 (output)
R/W (output)
READY (input)
Bus lock cycle
BCYST (output)
Note 3
Note 3
HLDRQ (input)
HLDAK (output)
D0-D15 (I/O)
(Read)
Notes 1.
A2-A27 (output) and BE0-BE3 (output)
2.
If the chip select function is not used, A28-A31 are output to CS0-CS3.
3.
Idle state
Remarks 1.
A broken line indicates high impedance.
2.
An arrow indicates a sampling timing.
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