參數(shù)資料
型號(hào)： μPD705100
廠商： NEC Corp.
英文描述： 32 Bit Microprocessor(32 位微處理器)
中文描述： 32位微處理器（32位微處理器）
文件頁(yè)數(shù)： 45/81頁(yè)
文件大小： 441K
代理商： ΜPD705100
45
CHAPTER 5 16-BIT BUS MODE
CHAPTER 5 16-BIT BUS MODE
If the SIZ16B input, sampled at reset, is active, the external bus width becomes 16 bits (16-bit bus mode).
In this mode, the low-order 16 bits (D0-D15) of the data bus are valid, BE2/BH acts as BH and BE3/A1 acts
as A1. The high-order 16 bits (D16-D31) of the data bus enter the high-impedance state.
5.1 16-BIT BUS SIZING
The V830 has a bus sizing function by which, to enable access from the data bus to 16 bits of memory or
the I/O space, data can be transferred using only the low-order 16 bits of the 32-bit data bus.
When the SIZ16B input is activated upon a reset, the external data bus width becomes 16 bits (16-bit bus
mode). In 16-bit bus mode, D16-D31 are all set to the high-impedance state and BE0, BE1, BH, and A1 are
output in a way suited to a 16-bit bus system. Connection to D16-D31 is not necessary. The SIZ16B input
can be changed only when the V830 is reset. It cannot be changed at any other time.
5.1.1 Byte/Halfword Access
Bus cycles in either of two bus states (Ta and Ts) are used for byte/halfword access.
(1) Upper halfword
During read cycles, data is read from D0-D15.
During write cycles, D16-D31 data read from the write buffer is output to D0-D15.
Figure 5-1 illustrates the operation for upper halfword access. In this figure, B indicates the upper halfword
(high-order 16 bits of the word).
Figure 5-1. Upper Halfword Access
Read cycle
Write cycle
Read buffer
31
Write buffer
31
Internal
operation
unit
Data bus
Internal
operation
unit
Data bus
B
0
16
15
16
15
0
31
B
0
16
15
16
15
0
31
B
B
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